Variable clock delay circuit

Details Variable clock delay circuit Variable clock delay circuit

1991-06-17

1992-06-30

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 45, H03B 2700, H03L 706, H03L 7099

Patent

active

051266911

ABSTRACT:
A variable clock delay circuit provides a clock output signal (CLKOUT) whose phase can be varied with respect to an incoming reference signal (REFIN). A voltage controlled ring oscillator (24) having a plurality of delay stages (26-33) locks to a predetermined factor of the frequency of the incoming reference signal. A multiplexer circuit (14) selectively provides a signal (or its inversion thereof) appearing at a selected input of any one of the plurality of delay stages to its output. A divider circuit (16) divides the signal appearing at the output of the multiplexer circuit by the predetermined factor to obtain the clock output signal whose frequency is substantially equal to the frequency of the incoming reference signal and whose phase can be adjusted with respect to the incoming reference signal.

REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 4706040 (1987-11-01), Mehrgardt
A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-.mu.m CMOS, by: Kim, Helman and Gray.
Design of PLL-Based Clock Generation Circuit, by: Jeong, Borriello, Hodges and Katz.
A Monolithic CMOS 10 MHz DPLL for Burst-Mode Data Retiming, by: Sontag and Leonowich.
Gazelle Part GA1110.

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