Variable bit width cache memory architecture

Details Variable bit width cache memory architecture Variable bit width cache memory architecture

1997-01-03

1999-01-19

Elmore, Reba I.

Excavating

371 43, 711118, 711144, G11C 2900

Patent

active

058621547

ABSTRACT:
A system and method of efficiently transferring a cache line of data between a cache memory to a processor. A first group of M words is transferred between the cache memory and the processor in a first cache transfer cycle, where the first group of M words includes a tag word and M-1 words from the plurality of data words in the cache line. A second group of M words is transferred between the cache memory and the processor in a second cache transfer cycle, where the second group of M words includes M additional words from the plurality of data words. The process continues until the entire cache line has been transferred between the cache memory and the processor.

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