Variable access frame buffer memory

Details Variable access frame buffer memory Variable access frame buffer memory

1985-04-05

1988-05-03

Harkcom, Gary V.

Boots, shoes, and leggings

340799, 365230, G11C 800

Patent

active

047424745

ABSTRACT:
A frame buffer memory comprises a set of memory chips arranged in an array of n rows (planes) and m columns. All memory chips are identically addressed, a set of m, n-bit pixels being stored at each memory address with one bit of each pixel being stored in each array plane. Each memory chip of each column is row address strobed by a common row address strobe line while each memory chip of each plane is column address strobed by a common column address strobe line. By appropriately strobing selected row and column address lines, data may be written to the memory array on a pixel-by-pixel or plane-by-plane basis with such data being written to individual pixels or planes or to blocks of pixels or planes. Combinational logic within the frame buffer memory permits pixel data to be rapidly modified according to preselected rules during a memory write operation prior to being written into memory.

REFERENCES:
patent: 3404382 (1968-10-01), Rosenheck et al.
patent: 4564926 (1986-01-01), Nikaido et al.
patent: 4597063 (1986-06-01), Takemae
patent: 4618858 (1986-10-01), Belch
patent: 4644503 (1987-02-01), Bantz et al.

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