Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – In voltage variable capacitance diode
Reexamination Certificate
2002-01-11
2004-02-03
Thompson, Craig (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
In voltage variable capacitance diode
C257S595000
Reexamination Certificate
active
06686640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a varactor having variable capacitance and a method of fabricating the same, and more particularly, to a varactor having an improved Q-factor and a method of fabricating the same using a silicon-germanium (SiGe) heterojunction bipolar transistor.
2. Description of the Related Art
Generally, varactors are devices whose reactance components vary with applied voltages or current sources, and more particularly, denote devices which change their reactance components using the fact that the width of a depletion area changes depending on the magnitude of reverse bias applied to a pn junction.
When varactors are used in fields requiring a high Q-factor, a resistance component parasitic on a variable reactance value should be maintained minimum in order to achieve excellent operating characteristics. Particularly, in designing voltage-controlled oscillators capable of varying oscillation frequency using control voltage, together with the Q-factor of an inductor, the Q-factor of a varactor is one of the essential factors influencing the Q-factor of a resonator in a voltage-controlled oscillator and the phase noise of an oscillation signal.
There has been proposed a technique using an accumulation mode and a depletion mode by using a gate oxide layer of a complementary metal-oxide semiconductor (CMOS) transistor in fabricating a varactor having a high Q-factor (J. N. Burghartz; IEEE Journal of Solid-State Circuits, Vol. 32, No. 9, 1997, pp1440-1445). However, disadvantageously, this method requires use of processes of fabricating a CMOS transistor or bipolar CMOS (BiCMOS) transistor in order to form a gate oxide layer of a CMOS transistor. Particularly, in the case of CMOS transistors, noise occurs on the interface between oxide layers due to structural problems, which increases the 1/f (frequency) noise of a device. As a result, the phase noise of a voltage-controlled oscillator increases.
Recently, a method of fabricating a varactor using a SiGe heterojunction bipolar transistor (HBT) has been highlighted. It has been widely known that a SiGe HBT achieves excellent performance by decreasing an energy band gap in a base region.
FIG. 1
is a sectional view of a typical SiGe HBT, particularly, a typical self-alignment type SiGe HBT. Referring to
FIG. 1
, an n
+
-type buried collector region
101
is formed in the upper surface portion of a p-type substrate
100
. An n-type collector region
102
and an n
+
-type collector contact region
103
are formed on the n
+
-type buried collector region
101
such that they are separated by an isolation layer
104
. A p
+
-type SiGe base region
105
is thinly formed on the n-type collector region
102
to extend over the isolation layer
104
. An n
+
-type polysilicon layer is formed on the surface of the p
+
-type SiGe base region
105
and the surface of the n
+
-type collector contact region
103
. The n
+
-type polysilicon layer on the p
+
-type SiGe base region
105
is an n
+
-type emitter region
106
and the n
+
-type polysilicon layer on the n
+
-type collector contact base region
103
is a collector conductive layer
107
.
The p
+
-type SiGe base region
105
electrically contacts a base electrode
109
, the n
+
-type emitter region
106
electrically contacts an emitter electrode
110
, and the collector conductive layer
107
electrically contacts a collector electrode
111
. A titanium silicide layer
112
is disposed between each of the regions
105
,
106
, and
107
and each of the electrodes
109
,
110
, and
111
. The electrodes
109
,
110
, and
111
are insulated from one another by an insulation layer
113
. Reference numeral
114
denotes an impurity region for isolating devices. Reference numeral
115
denotes a p
+
-type external base region.
FIG. 2
is a sectional view of a varactor using the self-alignment type SiGe HBT of FIG.
1
. In
FIGS. 1 and 2
, the same reference numerals denote the same regions or layers.
In comparison with the self-alignment type SiGe HBT of
FIG. 1
, an n
+
-type emitter region
106
is electrically isolated from a p
+
-type base region
105
by an insulation layer
113
to form a pn diode structure, and the emitter electrode
110
of
FIG. 1
is eliminated. Accordingly, an n
+
-type buried collector region
101
and a collector electrode
111
act as a cathode region and a cathode electrode, respectively. The p
+
-type base region
105
and a base electrode
109
act as an anode region and an anode electrode, respectively.
However, in such a varactor, although the p
+
-type base region
105
contacts the base electrode
109
with a titanium silicide layer
112
therebetween, a parasitic resistance component still exists, which may badly affects the Q-factor of a device. In addition, when a plurality of varactors are implemented in a multi-finger form, the n
+
-type buried collector region
101
is necessarily longer in order to secure the area for connecting the bases of the adjacent varactors. As a result, collector serial resistance increases, thereby decreasing the Q-factor. Moreover, parasitic capacitance, which is formed by the overlap of the base region
105
and a collector region
102
due to an isolation layer
104
, is connected to the intrinsic capacitance of the varactor in parallel, so entire capacitance increases.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is a first object of the present invention to provide a varactor having an excellent Q-factor maintained using a silicon-germanium (SiGe) heterojunction transistor having a good phase noise characteristic.
It is a second object of the present invention to provide a method of fabricating the varactor.
To achieve the first object of the invention, in a first embodiment, there is provided a varactor including a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.
Preferably, the varactor further includes a collector conductive layer and a metal silicide layer which are formed between the collector contact region and the second electrode layer. Here, the collector conductive layer may be a polysilicon layer doped with impurity ions of the second conductivity type at a high concentration.
Preferably, the varactor further includes a high-concentration external base region of the first conductivity type formed between the collector region and the silicon-germanium base region.
In a second embodiment, there is provided varactor including a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a conductive layer formed on the silicon-germanium base region, a metal silicide layer formed on the conductive layer, a first electrode layer formed to co
Kang Jin-Yeong
Mheen Bong-ki
Suh Dong-woo
Blakely & Sokoloff, Taylor & Zafman
Electronics and Telecommunications Research Institute
Thompson Craig
LandOfFree
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