Active solid-state devices (e.g. – transistors – solid-state diode – Voltage variable capacitance device – With specified dopant profile
Reexamination Certificate
2001-05-24
2003-11-25
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Voltage variable capacitance device
With specified dopant profile
C257S344000, C257S408000, C257S595000
Reexamination Certificate
active
06653716
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor varactors and, more particularly, to a varactor and a method of forming a varactor with an increased linear tuning range.
2. Description of the Related Art
A varactor is a semiconductor device that has a voltage-controlled capacitance. As a result, the capacitance across the device varies as the voltage across the device varies. Varactors are commonly used in the voltage-controlled oscillator (VCO) circuits of phase-locked loops (PLLs) which, in turn, are commonly used in high-frequency applications, such as with cellular phones.
FIG. 1
shows a cross-sectional diagram that illustrates a conventional NMOS varactor
100
. As shown in
FIG. 1
, varactor
100
, which is formed in a p− substrate
110
, includes a n− well
112
that is formed in substrate
110
, and an n+ diffusion region
114
which is formed in n− well
112
. N-well
112
, in turn, is defined to have a lower-plate region
116
that adjoins n+ diffusion region
114
. In addition, varactor
100
also includes a layer of gate oxide
120
that is formed on n− well
112
over lower-plate region
116
, and an upper-plate gate
122
that is formed on gate oxide layer
120
.
FIG. 2
shows a graph
200
that illustrates the operation of varactor
100
. Graph
200
utilizes a line C
CONVENTIONAL
to identify the capacitance (C) across varactor
100
for a voltage V across varactor
100
. As shown in
FIG. 2
, when the voltage V across varactor
100
ranges from a negative value to a positive value, the capacitance C across varactor
100
increases. For example, when ground is applied to n+ diffusion region
114
and a voltage ranging from −0.5V to +0.7 is applied to gate
122
, the capacitance C increases from approximately 7.7×10
−16
farads to approximately 1.7×10
−15
farads.
In addition, as further shown in
FIG. 2
, varactor
100
also has a substantially linear region of operation. For example, when ground is applied to n+ diffusion region
114
and a voltage ranging from −0.25V to +0.25V is applied to gate
122
, the capacitance C substantially linearly increases from approximately 9.0×10
−16
farads to approximately 1.5×10
−15
farads as shown by line C
CONVENTIONAL
.
FIGS. 3A-3B
shows cross-sectional diagrams that illustrate the operation of varactor
100
at the linear endpoints. As shown in
FIG. 3A
, when ground is applied to n+ diffusion region
114
and the lower linear endpoint of −0.25V is applied to upper-plate gate
118
, the negative voltage causes a depletion region
310
to be formed in the lower-plate region
116
of n− well
112
. The capacitance of varactor
100
in this condition is defined by the thickness of gate oxide layer
120
and the charge on lower-plate region
116
which, in turn, is defined by depletion region
310
.
By contrast, as shown in
FIG. 3B
, when ground is applied to n+ diffusion region
114
and the upper linear endpoint of +0.25V is applied to upper-plate gate
118
, the positive voltage causes a negative charge
312
to collect (or accumulate) in the lower-plate region
116
of n− well
112
. Thus, as shown in
FIGS. 3A and 3B
, the capacitance of varactor
100
varies with the voltage across varactor
100
because as the voltage on gate
122
is varied, the charge level present in the lower-plate region
116
of n− well
112
also varies.
One of the advantages of varactor
100
is that varactor
100
can easily be integrated into a standard CMOS or BiCMOS fabrication process. N− well
112
can be formed at the same time that the wells for the PMOS transistors are formed, while n+ diffusion region
114
can be formed at the same time that the source and drain regions for the NMOS transistors are formed. In addition, gate oxide layer
120
and gate
122
can be formed at the same time that the oxide layer and MOS gates are formed.
One of the disadvantages of varactor
100
is that varactor
100
provides a relatively small linear tuning range, ranging only from approximately 9.0×10
−16
farads to approximately 1.5×10
−15
farads. If a greater or lesser amount of capacitance is required, a more complicated structure is required. As a result, there is a need for a varactor with a larger linear tuning range that remains easily integratable into a standard CMOS or BiCMOS fabrication process.
SUMMARY OF THE INVENTION
The present invention provides a varactor and a method of forming a varactor with an increased linear tuning range that remains easily integratable into a standard CMOS or BiCMOS fabrication process. The varactor of the present invention includes a first semiconductor material of a first conductivity type that has a lower-plate region.
The varactor also includes a first diffusion region of a second conductivity type that is formed in the first semiconductor material. The first diffusion region adjoins the lower-plate region. The varactor further includes a second diffusion region of the first conductivity type that is formed in the first semiconductor material. The second diffusion region adjoins the first diffusion region, and has a dopant concentration that is greater than a dopant concentration of the first semiconductor material.
The varactor of the present invention additionally includes a layer of insulation material that is formed on the first semiconductor material, and a varactor gate that is formed on the layer of insulation material over the lower-plate region.
The present invention also provides a method of forming a varactor in a first semiconductor material of a first conductivity type that has a lower-plate region. The method includes the steps of forming a layer of isolation material over the first semiconductor material, and forming a layer of first material over the layer of isolation material.
The method further includes the steps of etching the layer of first material to form a varactor gate on the layer of isolation material over the lower-plate region, and forming a first diffusion region in the first semiconductor material to adjoin the lower-plate region. The first diffusion region has a second conductivity type.
The method additionally includes the steps of forming a spacer over the first diffusion region that adjoins the varactor gate, and forming a second diffusion region in the first semiconductor material to adjoin the first diffusion region. The second diffusion region has the first conductivity type and a dopant concentration that is greater than a dopant concentration of the first semiconductor material.
REFERENCES:
patent: 5338966 (1994-08-01), Kasahara
patent: 6225674 (2001-05-01), Lim et al.
patent: 6320474 (2001-11-01), Kamiya et al.
Francis Pascale
Hopper Peter J.
Vashchenko Vladislav
National Semiconductor Corporation
Ngo Ngan V.
Pickering Mark C.
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