Vapor phase connection techniques

Details Vapor phase connection techniques Vapor phase connection techniques

2000-08-11

2004-01-13

Arbes, Carl J. (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S846000, C029S852000, C029S853000

Reexamination Certificate

active

06675469

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to microelectronic components and fabrication of microelectronic components.
BACKGROUND OF THE INVENTION
Numerous microelectronic components incorporate insulating or “dielectric” layers and conductors extending through such layers. The directions along the surfaces of the layers are commonly referred to as “horizontal” directions, whereas the direction through the layers is commonly referred to as the “vertical” or “z” direction. The conductors extending through the layers are commonly referred to as z-direction conductors or “vias”. For example, a multilayer microelectronic circuit panel may include several dielectric layers. Each dielectric layer has conductors extending along one or both surfaces of the layer in horizontal directions and has vias extending through the layer to connect certain conductors on opposite sides of the panel with one another. Typically, such a multi-layer circuit is fabricated by a sequential process. Each dielectric layer is deposited on previously-formed dielectric layers and the processes needed to form the vias and the horizontal conductors are performed. Such a sequential build-up process suffers from numerous drawbacks, including significant loss of productivity caused by quality problems. If any defect occurs in formation of a later layer, the entire multi-layer structure must be discarded.
As taught in certain preferred embodiments of commonly assigned U.S. Pat. Nos. 5,367,764 and 5,282,312, multi-layer circuit panels can be fabricated using a parallel processing approach. In this approach, the various panels constituting the multi-layer structure are fabricated separately and then stacked together with interposers incorporating a curable dielectric material such as an epoxy and also incorporating masses of electrically conductive joining material such as solder extending through the interposer at predetermined locations. The stacked assembly is then cured as, for example, under heat and pressure. The dielectric material joins the circuit panels to one another and the electrically conductive material forms conductive pathways between conductors on the various panels. Because the individual panels can be tested prior to assembly, defects in the panel manufacturing process do not result in loss of the entire assembly. Also, as further explained in the aforementioned '764 and '312 patents, the individual panels can be selectively treated so that vertical connections between panels are made only at certain locations.
Other processes involving parallel production of multiple circuit panels and assembly in a stack are taught in certain preferred embodiments of co-pending, commonly assigned PCT Application PCT/US97/23948, published as International Publication WO 98/26476 and U.S. Pat. No. 5,590,460. As taught in certain preferred embodiments of the '460 patent and '948 PCT application, multiple circuit panels can be stacked and electrically interconnected with one another and mechanically engaging features on the circuit panels with features of conductive elements carried on interposer layers.
These approaches offer useful solutions to the encountered in fabrication of multi-layer problems. However, even with these improvements, the circuit panels typically still include vias extending through dielectric layers. Such vias commonly are formed by providing holes in the dielectric layers and depositing a conductive metal in the dielectric layers by processes such as electroless plating and electroplating. These processes work well with relatively large vias. However, it would be desirable to provide smaller vias so as to make the entire assembly more compact. It is difficult to form relatively small vias, such as circular vias having diameters less than about 60 microns and, more particularly, less than about 25 microns by plating.
Various proposals have been advanced for depositing conductive materials into holes to form vias by techniques other than plating. Cranston, et al., U.S. Pat. No. 3,562,009 shows a process for forming “metalized through-holes” by positioning a metallic element at a lower surface of a substrate having a hole formed therein and directing a laser beam or electron beam from above the substrate through the open top end of the hole onto the metal, thereby evaporating the metal onto the walls of the hole. In other embodiments, this reference discloses directing a similar beam onto a mass of powdered material disposed within the hole. This method suffers obvious drawbacks as a production technique, including the need to direct a powerful beam sequentially onto various locations on the substrate and hold the beam at each location for a time sufficient to vaporize the material. Moreover, this method is useful only to process a single substrate at a time. Beilin, et al., U.S. Pat. No. 5,454,161 discloses metal organic chemical vapor deposition (“MOCVD”) of metal into openings of a dielectric layer. In the MOCVD process, the substrate is held in the reaction chamber so that openings of the holes are exposed to the interior of the reaction chamber. A metal-containing gaseous composition is introduced into the chamber. The composition decomposes to deposit metal in the open vias. Yamaguchi, et al., U.S. Pat. No. 5,589,668, discloses a similar process using vapor deposition methods such as evaporation, ion plating, or sputtering. In all of these processes, the substrate is held within a chamber so that openings of the vias are open to the interior of the substrate. Each substrate must be held within a relatively complex and expensive treatment apparatus for a time sufficient to build up the required metallic layer within its vias. Moreover, stacked substrates cannot be treated. U.S. Pat. No. 4,933,045 refers to metalization of vias by “evaporation, sputtering or plating” as assertedly “well-known in the art” but does not offer further details of such processes. Despite these attempts to use vapor deposition for forming vias, there is still need for better useful and economical vias-forming process.
Another common problem encountered in fabrication of microelectronic assemblies is mounting and connecting one component to another. For example, a semiconductor chip or other microelectronic device typically must be connected to a circuit panel. As described in certain preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265, 5,148,266 and 5,347,159, the contacts of a semiconductor chip may be electrically connected to terminals on a small circuit panel or connection component overlying a face of the chip itself. The terminals on the connection component in turn are connected to contact pads on a substrate such as a circuit panel. Desirably, the connection component is movable with respect to the chip to accommodate dimensional changes caused by thermal effects during manufacture and/or use. The connections between the chip contacts and the interposer can be made by various methods. For example, these connections can be made by wire-bonding or by techniques such as thermosonic or ultrasonic bonding of pre-fabricated leads on the interposer to the chip contacts. Further improvements in lead bonding are taught, for example, in U.S. Pat. Nos. 5,536,909, 5,787,581 and PCT International Publication 94/03036. These processes provide marked improvements in chip connection processes and in the resulting assemblies.
In a process known as flip-chip bonding, contacts on the chip are bonded directly to contact pads on a substrate such as a circuit board using solder balls. All of the contacts of the chip may be connected simultaneously. However, flip-chip bonding requires considerable spacing between contacts on the chip to accommodate the solder balls and suffers from other drawbacks including susceptibility to thermal stresses.
As described in U.S. Pat. No. 5,518,964, numerous connections on a semiconductor chip or wafer can be made simultaneously by superposing an element such as a dielectric substrate having leads thereon with the chip or wafer bonding tip ends of

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