Value-strength based test pattern generator and process

Details Value-strength based test pattern generator and process Value-strength based test pattern generator and process

1988-09-30

1991-04-30

Smith, Jerry

Excavating

371 23, G06F 1110

Patent

active

050124714

ABSTRACT:
An automatic test pattern generator and process assigns value-strength number to selected nodes representing the electrical characteristic strength of integrated circuits including field effect transistors and the logic state values at those nodes. These value-strength numbers become sensitized to the inputs of the selected node and become propagated to outputs of the selected node for establishing patterns for test signals. The test signals later become used in chip testers for determining good and bad integrated circuit chips. The value-strength numbers also become used in dynamic testing of the integrated circuit nodes by using clock signals of the integrated circuit to establish a transition at a start node of a test path. Within a known clock period later, the transition should become captured at an end node of the test path.

REFERENCES:
patent: 3916306 (1975-10-01), Patti
patent: 4204633 (1980-05-01), Goel
patent: 4696006 (1987-09-01), Kawai
patent: 4716564 (1987-12-01), Hung
C. Salzmann, "Automatic Test Sequence Generation", IEEE Conference, Arlington, Tex., 11/1976, pp. 112-116.
P. Goel, "Dynamic Subsumation of Test Patterns for LSSD Systems", IBM TDB, vol. 21, No. 7, 12/1978, pp. 2782-2784.
P. Goel, "RAPS Test Pattern Generator", IBM TDB, vol. 21, No. 7, 12/1978, pp. 2787-2791.
C. Cha et al., "9-V Algorithm for Test Pattern Generation . . . ", IEEE Trans. on Comp., vol. C-27, No. 3, 3/1978, pp. 193-200.

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