Validity checking arrangement for extended memory mapping of ext

Details Validity checking arrangement for extended memory mapping of ext Validity checking arrangement for extended memory mapping of ext

1983-06-22

1985-07-23

Smith, Jerry

Excavating

371 57, G06F 1100

Patent

active

045312150

ABSTRACT:
In a telecommunications switching system, a CPU utilizes memory mapped access to a number of duplex external devices and other memories. A validity checking arrangement provides for detecting invalid external device unit numbers for memory mapped accesses by the CPU. In addition, this validity checking arrangement will determine that the CPU's operating software has attempted a memory mapped access with an invalid unit number or that a true hardware fault exists.

REFERENCES:
patent: 3449717 (1969-06-01), Smith et al.
patent: 3737577 (1973-06-01), Birkin
patent: 3781792 (1973-12-01), Birkin
patent: 3978449 (1976-08-01), Sanders et al.
patent: 4138599 (1979-02-01), Munter
patent: 4155073 (1979-05-01), Ulch et al.

Affiliated with

Also associated with

Rating

Validity checking arrangement for extended memory mapping of ext does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Validity checking arrangement for extended memory mapping of ext, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Validity checking arrangement for extended memory mapping of ext will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-637331