Validation of RAM-resident software programs

Details Validation of RAM-resident software programs Validation of RAM-resident software programs

1992-12-31

1994-10-18

Ruggiero, Joseph

Excavating

371 377, G06F 1110

Patent

active

053575270

ABSTRACT:
A method for transmitting and verifying the accuracy of a software program, expressed as a stream of J bits.. A first forward error correction error coding, detection and correction (ECDC) procedure is applied to the program, where the first ECDC procedure is expressible as a stream of K1 error coding bits plus L1 additional bits representing the procedure for determining the values of the K1 bits and for detecting the presence of and correcting an error in the original stream of J bits plus the K1 error coding bits, as received by a recipient. A second ECDC procedure is then applied to the K1+L1 bits used in the first ECDC program, where the second ECDC procedure is expressible as a stream of K2 error coding bits plus L2 additional bits representing the procedure for determining the values of the K2 bits and for detecting the presence of and correcting an error in the (K1+L1}bits that represent the first ECDC procedure. This second ECDC procedure is applied to check the accuracy of transmission of the bits representing the first ECDC procedure, which is applied to the software program itself. The bit stream of J bits can be decomposed into 8 or 16 mutually exclusive subsidiary bit streams, to each of which the above error checking procedure is applied, to take advantage of certain kinds of error statistics that may be present.

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patent: 4748628 (1988-05-01), Moriwaki
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