Validating the synchronization of lock step operated circuits

Details Validating the synchronization of lock step operated circuits Validating the synchronization of lock step operated circuits

1995-02-27

1997-02-18

Beausoliel, Jr., Robert W.

Excavating

371 223, 39518306, G01R 3128, G06F 1100

Patent

active

056047541

ABSTRACT:
Apparatus for and methods of detecting an error in multiple state lock step operated circuits. Signatures representing internal states of each circuit are conveyed in daisy chain format to connect successive circuits. Local comparisons between the received signatures and those representing previous internal states are used to detect mismatches between states. Signals indicating the detection of a mismatch appear on a commonly connected error line. Scanned comparison of the circuits to determine those having detected a mismatch allows the error source to be identified.

REFERENCES:
patent: 3916380 (1975-10-01), Fletcher et al.
patent: 4541094 (1985-09-01), Stiffler et al.
patent: 5331274 (1994-07-01), Jarwala et al.
patent: 5452443 (1995-09-01), Oyamada et al.
patent: 5487074 (1996-01-01), Sullivan
IBM TDB, "Using the Residue Function as a Chip to Chip Synchronization Check" vol. 37, No. 7, Jul. 1994, pp. 509-510.

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