Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-04-27
2002-01-15
Mills, Gregory (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C118S722000, C118S719000, C438S709000, C438S715000, C438S706000, C156S345420
Reexamination Certificate
active
06339028
ABSTRACT:
BACKGROUND ART
1. Field of the Invention
The present invention relates to vacuum plasma etching devices in which semiconductor wafers having photo-resist patterns are exposed to a vacuum plasma etching process to etch integrated circuits (“IC”) into the semiconductor wafers. More particularly, the present invention relates to a vacuum plasma etching device and a method for curing the photo-resist patterns with an ultraviolet bake prior to the plasma etching process to improve CD dispersion, enhance pattern transfer, and prevent photo-resist reticulation.
2. Description of Related Art
Vacuum plasma etching systems and devices for etching high-density IC's onto semiconductor wafers prepared with a photo-resist pattern are well known in the art. These semiconductor wafers, or substrates, are typically made of silicon. It is common to dispose a layer of metallic material on top of the semiconductor wafer, into which various elements, such as interconnect lines, holes for vertical interconnect lines, vias, and contacts are lithographically transferred. These interconnecting elements are etched to form the components of the desired IC, such as transistors. The photo-resist patterns define where the plasma will etch away the metallic films.
A typical example of a vacuum plasma etching device is the poly etch device sold by Lam Research of Fremont, Calif., under model number 4420. In such a device, an individual semiconductor wafer is taken from a loading cassette of unetched semiconductor wafers, fed into an entrance vacuum loadlock that is pumped down to a vacuum, passed into a vacuum reaction chamber where the plasma etching process takes place, passed into an exit vacuum loadlock where the vacuum is released, and then fed into a finished cassette of etched semiconductor wafers. Although the total elapsed time, from taking an unetched semiconductor wafer out of the loading cassette to placing the etched semiconductor wafer into the finished cassette, varies, the time required for the plasma etching process within the vacuum reaction chamber usually takes more than 60 seconds. Thus, there is a process cycle of at least 60 seconds. During this process cycle the next semiconductor wafer to be etched is held within the entrance vacuum loadlock. Although a portion of this time is used to pump the entrance loadlock down to a vacuum, for the majority of the process cycle, the semiconductor wafer sits idly in a vacuum in the entrance vacuum loadlock.
Prior to performing the plasma etching process on the semiconductor wafers, it is desirable to expose the semiconductor wafers to ultraviolet light to “cure” the photo-resist pattern. Normally, this is done in a separate device than the vacuum plasma etching device. This ultraviolet curing process makes the resist pattern more resistant to the plasma etch and helps preserve the pattern integrity during the plasma etching process. The presence of a vacuum during this curing process helps to remove volatile substances present in the photo-resist, thereby further “hardening” the photo-resist against the plasma etching process. Curing the photo-resist pattern with ultraviolet light improves CD dispersion, enhances pattern transfer, and prevents photo-resist reticulation.
Despite these advances in the art, there is a need for a plasma etching device that increases efficiency, increases productivity, improves CD dispersion, enhances pattern transfer, and prevents photo-resist reticulation. There is a need for an improved plasma etching device that not only performs a vacuum plasma etching process on a semiconductor wafer, but which can also perform an ultraviolet bake on the semiconductor wafer prior to the plasma etching process to cure the photo-resist pattern on the semiconductor wafer.
BRIEF SUMMARY OF THE INVENTION
A principle advantage of the present invention is that the unused time in which a semiconductor wafer is held within a vacuum plasma etching tool loadlock prior to being plasma etched can be efficiently used to cure the photo-resist pattern on the semiconductor wafer by selectively exposing the photo-resist pattern to ultraviolet light. The device and method of the present invention exposes the photo-resist pattern to ultraviolet light and cures the photo-resist pattern, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation.
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Excerpts from catalog of Lam Research of Freemont, California for Vacuum Plasma Etching Device.
Excerpts from catalog of Lam Research of Freemont, California for Vacuum Plasma Etching Device Model No. 4420, No Date Available.
Hassonzadeh P.
Jorgenson Lisa K.
Mills Gregory
Munck William A.
STMicroelectronics Inc.
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