V.sub.P -corrected offset voltage trim

Details V.sub.P -corrected offset voltage trim V.sub.P -corrected offset voltage trim

1990-12-14

1991-10-08

Prenty, Mark

357 22, 357 13, H01L 2702, H01L 2980, H01L 2990

Patent

active

050559028

ABSTRACT:
A trim arrangement for adjusting a differential input stage in a BIFET.RTM. integrated circuit is presented wherein the trimming is done at wafer probing in the manufacturing process. Trim JFETs are invoked by means of reverse biased zener diodes which can be zapped thereby to achieve trimming in the conventional manner. The trim JFETs are ratioed in size so that the trim is V.sub.P compensated over a relatively broad range. An improved trim structure is presented wherein the offset trim is V.sub.P compensated and operated in a manner that renders its effect on the circuit constant and independent of the conventional load trim.

REFERENCES:
patent: 4176368 (1979-11-01), Compton
patent: 4496963 (1985-01-01), Dunkley et al.
patent: 4618833 (1986-10-01), Russell

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