Patent
1979-01-26
1980-09-30
Wojciechowicz, Edward J.
357 23, 357 41, 357 45, H01L 2906
Patent
active
042258790
ABSTRACT:
This disclosure relates to a V-MOS field effect transistor which is provided with enhanced source capacitance to provide a single transistor dynamic memory cell. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor.
REFERENCES:
patent: 4003036 (1977-01-01), Jenne
patent: 4119996 (1978-10-01), Jhabuala
Burroughs Corporation
Fassbender Charles J.
Peterson Kevin R.
Wojciechowicz Edward J.
Young Mervyn L.
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