V-groove isolated integrated circuit memory with integral pinche

Details V-groove isolated integrated circuit memory with integral pinche V-groove isolated integrated circuit memory with integral pinche

1975-04-10

1976-09-07

Larkins, William D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307238, 357 50, 357 51, 357 55, 357 60, H01L 2704

Patent

active

039796124

ABSTRACT:
A semiconductor integrated circuit having microminiature active and/or passive elements in which a crystallographic surface of a semiconductor body lies in the [100] crystallographic plane and anisotropically etched regions with sloped [111] crystallographic surface walls isolate adjacent semiconductor elements and/or define the boundaries of junctions and/or resistance regions formed in an epitaxial layer of said semiconductor body. The structure enables a subsurface region of the epitaxial layer to act as the dispersed collector of a transistor having a plurality of emitters and a subsurface epitaxial resistance interconnecting collector regions under different emitters such that one of the emitters acts with the collector and base as a transistor fed from a power supply through a relatively low resistance while the other emitter acts with the common base and a portion of the collector fed from the relatively high epitaxial resistor region beneath the base region to form a relatively low current drain transistor/resistor combination. A plurality of such transistors are cross coupled such that the transistors with high resistances in their collector circuits act as a latching multivibrator and the transistors with the low resistances in their collector circuits act as signal coupling transistors.

REFERENCES:
patent: 3482111 (1969-12-01), Gunderson et al.
patent: 3541531 (1970-11-01), Iwersen et al.
patent: 3631309 (1971-12-01), Myers
patent: 3659160 (1972-04-01), Sloan et al.
patent: 3818289 (1974-06-01), Mudge et al.

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