UV methods for screening open circuit defects in CMOS integrated

Details UV methods for screening open circuit defects in CMOS integrated UV methods for screening open circuit defects in CMOS integrated

1998-03-25

2000-08-22

Nguyen, Vinh P.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324501, 324752, G01R 3100

Patent

active

061078174

ABSTRACT:
A method for detecting defects in a CMOS integrated circuit. In one embodiment, an integrated circuit is exercised to a first cycle. IDDQ testing is then performed on the integrated circuit. Next, the integrated circuit is irradiated with for example ultraviolet radiation, which in one embodiment sets floating gates to an intermediate operating value. Next, IDDQ testing is performed again and any differences in IDDQ between the two IDDQ test measurements may be attributed to floating gate defects in the integrated circuit.

REFERENCES:
patent: 4736159 (1988-04-01), Shiragasawa et al.
patent: 4837506 (1989-06-01), Patterson
patent: 4967152 (1990-10-01), Patterson
patent: 5150043 (1992-09-01), Flesner
patent: 5334540 (1994-08-01), Ishii
patent: 5420522 (1995-05-01), Smayling
patent: 5640099 (1997-06-01), Sanada
patent: 5790565 (1998-08-01), Sakaguchi
patent: 5804980 (1998-09-01), Nikawa

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