Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-05-26
2004-02-03
Jones, Hugh (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06687661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns design of integrated circuits (ICs) and particularly relates to use of metal layer dependent attributes in a technology-independent description of an IC design.
2. Description of the Related Art
FIG. 1
provides a simplified cross-sectional view of a typical integrated circuit chip (or die)
50
. As shown in
FIG. 1
, chip
50
includes a semiconductor substrate
59
, metal layers
51
to
54
, electrically insulating layers
56
, and passivation layer
58
. Semiconductor substrate
59
, which is typically polysilicon, is used for forming the transistors and other electronic devices and may also be used for routing some of the electrical connections between these devices. However, wire routing occupies substrate space which otherwise could be used for the electronic devices. As a result, ordinarily only the shorter electrical connections are formed on substrate
59
. For the remainder of the connections, metal layers
51
to
54
are provided.
Metal layers
51
to
54
may be formed from any of a variety of materials including aluminum, copper or an electrically conductive alloy. Typically, two to four metal layers are formed on top of substrate
59
. By routing wires in the metal layers
51
to
54
, electrical connections can be made without using valuable space on substrate
59
. Between metal layers
51
and
52
,
52
and
53
, and
53
and
54
, and between metal layers
51
and substrate
59
is an electrically insulating layer
56
, which typically is formed as an oxide film. Connections between any of metal layers
51
to
54
and semiconductor substrate
59
are made using interlayer holes called vias. Passivation layer
58
functions to prevent the deterioration of the electrical properties of the die caused by water, ions and other external contaminants, and typically is made of a scratch-resistant material such as silicon nitride and/or silicon dioxide.
Currently, systems containing hundreds of thousands or millions of interconnected transistors and other basic electronic devices can be implemented on the semiconductor substrate of a single IC chip. Each such electronic device and wire, when viewed in relation to the other components in the IC, must satisfy a variety of electrical and physical requirements. In order to produce such complicated designs in a timely and cost efficient manner, a highly structured multi-phase design cycle has evolved. A conventional design cycle generally includes production of an IC design specification for a desired system, generation of a technology-independent description of the system, synthesis of a gate-level description of a system based on the technology-independent description, gate-level verification and physical design. The IC design specification describes the system at a high level of abstraction. The technology-independent description describes a processing scheme, together with related timing considerations, which will perform according to the design specification. Gate-level synthesis selects specific electronic components from a technology library and specifies wire connections between those components so as to implement the processing set forth in the technology-independent description. Gate-level verification verifies feasibility of the gate-level design. Finally, the physical design phase performs physical cell layout and wire routing and then generates information for fabricating an IC die which implements the gate-level description.
Most commonly, the technology-independent description is written in a hardware description language (“HDL”) such as Very High-Speed IC (VHSIC) HDL, or “VHDL”. Typically, HDL code provides a well-defined, highly structured syntax for describing a system. Moreover, HDL permits signal processing functionality to be described without specifying the specific hardware required to implement the processing. Many aspects of writing HDL code have been treated in depth in the literature, such as in “VHDL For Designers”, S. Sjoholm and L. Lindh, Prentice Hall, 1997; “VHDL And AHDL—Digital System Implementation”, F. Scarpino, Prentice Hall 1998; and “VHDL—Analysis and Modeling of Digital Systems”, Z. Navabi, McGraw-Hill 1998. These references are incorporated by reference herein as though set forth in full.
VHDL, in particular, allows a designer to describe a system using a functional description (e.g., using a hierarchical arrangement of interconnected functional components), a behavioral description (e.g., using sequential program statements that are similar to those of a high-level programming language), a data-flow description (e.g., using synchronous and asynchronous state machines, data paths, arithmetic operators, and registers), which may include register transfer level (RTL) description, a logic level description (e.g., using Boolean algebra), or by using any combination of these different description types. VHDL provides a syntax which is very similar to that of a software programming language and includes basic design components (or design entities) that have well-defined inputs and outputs. More complicated components can be designed from these basic design components in much the same way that complicated functions are created from basic functions in software design. Once created, these new components can be re-used and employed in hierarchical designs.
Because HDL generally describes a system in terms of generic functionality without specifying particular electronic components, HDL is referred to herein, and frequently in the current literature as well, as being “technology independent”. In fact, however, those skilled in the art do not understand the term “technology-independent” in its most strictly literal sense. The mere fact that the HDL description is designed with a view toward implementation on an IC, rather than in some other technology (such as optical computing), often will influence how the description is structured. Moreover, in certain cases a particular HDL description can be tailored to some extent for a given family of technology. Therefore, as used herein, the term “technology-independent” is intended to mean that the description is not primarily linked to a particular hardware implementation. Accordingly, when creating a technology-independent description, the designer generally can ignore factors such as driving strength, component choice, fanout and, often, the more detailed timing considerations.
During the synthesis phase of the IC design cycle, the HDL code is mapped to actual electronic components selected from an available technology library, together with interconnections between those components. Typically, synthesis is performed using an automated software tool such as Design Compiler, produced by Synopsis, Inc. Therefore, synthesis of HDL code in IC design is often likened to compilation of source code in software development.
Gate-level synthesis is thus the first step of IC design in which actual physical components are specified. In order to maintain a feasible design, the actual physical properties of these components generally must be considered. For instance, gate-level synthesis typically considers factors such as gate delay, power consumption and driving strength. In addition, the physical properties of wires connecting the various electronic components also should be considered. In fact, as chip design has improved and as gates have become increasingly faster, wire delays have become even more critical than gate delays in IC design. In this regard, it has been estimated that as much as 70 to 80% of the total delay in certain integrated circuits is due to wire delay. However, as indicated above, the precise routing of a wire between any two electronic components ordinarily is not determined until the physical design phase, and therefore typically is not known during gate-level synthesis.
As a result, many conventional synthesis techniques use a generic wire load model and a generic wire area model for estimating wire capacitance and resistance, respectively. Spec
Graef Stefan
Sugasawara Emery
Jones Hugh
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
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