Utilizing a depletion mode FET operating in the triode region an

Details Utilizing a depletion mode FET operating in the triode region an Utilizing a depletion mode FET operating in the triode region an

1985-10-31

1987-04-28

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307304, 307310, 357 22C, 357 2312, H03K 1714, H03K 19094

Patent

active

046617264

ABSTRACT:
A temperature compensation system for semiconductor logic gates where the temperature compensation is accomplished by two depletion mode FET's in electrical series relationship is disclosed. One of the FET's is adapted to operate in its triode region of operation and the other in its saturation region of operation.

REFERENCES:
patent: 3436621 (1969-04-01), Crawford
patent: 3508084 (1970-04-01), Warner, Jr.
patent: 3828230 (1974-08-01), Nishizawa et al.
patent: 4069430 (1978-01-01), Masuda
patent: 4405870 (1983-09-01), Eden
patent: 4433257 (1984-02-01), Kinoshita
patent: 4450369 (1984-05-01), Schuermeyer
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4499416 (1985-02-01), Koike
patent: 4578694 (1986-03-01), Ariizumi et al.

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