Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-03-31
2002-06-11
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S763000, C257S765000
Reexamination Certificate
active
06404053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to a metallized integrated circuit structure, and particularly to a metallized interconnect structure situated on a semiconductor substrate assembly and methods for making.
2. The Relevant Technology
Current technology for metallization of an integrated circuit involves the forming of a conductive layer over the integrated circuit. A typical metallization process is one that is performed at the “back end of the line” which is after the formation of integrated circuits that are to be wired by the metallization process. A single conductive layer is often formed so that it is situated above the integrated circuit to be wired. After the conductive layer is formed, it is then patterned and etched into a shape of the desired wiring necessary to metallize the integrated circuit. Since the conductive layer is situated above the integrated circuit, the resultant metallization will also be above the integrated circuit in a “wring up” scheme.
Another type of metallization involves the formation of a conductive layer at least in part below the integrated circuit in a recess composed of an electrically insulative or dielectric material. Such a wiring scheme may be described as a “wiring down” scheme. The recess can be either a trench, a hole, or a via. Depending upon the aspect ratio of the recess, poor step coverage of the conductive layer within the recess may result. Voids in the conductive layer within the recess may also result when the conductive layer does not completely fill up the recess. Voids and poor step coverage can cause the integrated circuit to experience an electrical failure. The electrical failure can be experienced during fabrication of the integrated circuit or after a period of time that the integrated circuit has been in use, such as where electrical contact with the conductive layer in the recess has been lost because the material of the conductive layer moves.
It would be an advantage in the art to overcome the problems of poor step coverage and voids.
SUMMARY OF THE INVENTION
In accordance with the invention as embodied and broadly described herein, the present invention relates to the method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. A novel interconnect structure is also disclosed. The term substrate assembly is intended herein to mean a substrate having one or more layers or structures formed thereon. As such, the substrate assembly may be, by way of example and not by way of limitation, a doped silicon semiconductor substrate typical of a semiconductor wafer.
The interconnect structure is formed in a dielectric material situated on the substrate assembly of the semiconductor wafer. The novel process forms the dielectric material into a recess having a specified geometry shape. The shape formed in the dielectric material will preferably be a recess therein. The recess can be a trench, a hole, a via, or a combination of a trench and a hole or via. The dielectric shape can be formed by processing the dielectric material by way of dry etching or other recess-creating process.
Following the creation of the dielectric structure in the dielectric material, at least one diffusion barrier layer is formed over the dielectric structure. The diffusion barrier layer is at least partially conformably formed upon the dielectric structure. The material from which the diffussion barrier layer is substantially composed is preferably selected from the group consisting of ceramics, metallics, and intermetallics. More preferably, the diffusion barrier layer is substantially composed of a material that is selected from the group consisting of aluminum nitride, tungsten nitride, titanium nitride, and tantalum nitride.
A seed layer is then formed upon the diffusion barrier layer. The seed layer helps to promote nucleation, deposition, and growth of a material that will be used to fill up the dielectric structure. The seed layer can also serve the purpose of increasing surface mobility of the barrier layer which helps to make a desirable filling of the dielectric structure in the metallization process. Preferably, the material from which the seed layer is substantially composed is selected from the group consisting of ceramics, metallics, and intermetallics. More preferably, the material from which the seed layer is composed is selected from the group consisting of aluminum, titanium nitride, titanium, and titanium aluminide. Additionally and by comparison, the diffusion barrier layer will preferably be composed of a material having a melting point greater than or equal to that of the material from which the seed layer is composed
An electrically conductive layer is then formed upon the seed layer. The electrically conductive layer is the current carrier for electrical signals that will communicate with an integrated circuit associated therewith. Preferably, the electrically conductive layer is substantially composed of aluminum or copper. The material from which the diffusion barrier layer is composed will preferably have a melting point greater than that of a material from which the electrically conductive layer is composed. The material from which the seed layer is composed will preferably have a melting point greater than or equal to that of the material from which the electrically conductive layer is composed.
An energy absorbing layer is then formed upon the conductor layer. The energy absorbing layer will preferably have a greater thermal absorption capacity than that of the electrically conductive layer. Alternatively, the energy absorbing layer will preferably being composed of a material having a higher melting point than that of the material from which the electrically conductive layer is composed. As another alternative, the energy absorbing layer will preferably be composed of a material having both a higher thermal insulation capacity and electric insulation capacity than that of the material from which the electrically conductive layer is composed.
The energy absorbing layer is heated to cause the conductor layer to flow so as to fill voids that have formed within the dielectric structure. In conjunction with the heating of the energy absorbing layer, a pressure above atmospheric pressure can be applied to the semiconductor substrate assembly to better assist the process of causing the conductor layer to flow so as to fill voids within the dielectric structure. Preferably, the energy absorbing layer is substantially composed of a material selected from the group consisting of titanium, titanium nitride, tungsten, tungsten nitride, silicon nitride, silicon dioxide, tantalum, tantalum nitride, and carbon.
Following the steps of heating or heating and pressurizing the energy absorbing layer, the energy absorbing layer is removed, preferably by planarizing. The planarizing step may also remove a portion of the conductive layer situated above the dielectric structure.
REFERENCES:
patent: 4472456 (1984-09-01), Shah
patent: 4700465 (1987-10-01), Sirkin
patent: 4997518 (1991-03-01), Madokoro
patent: 5274210 (1993-12-01), Freedman
patent: 5380678 (1995-01-01), Yu et al.
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5409862 (1995-04-01), Wada et al.
patent: 5420072 (1995-05-01), Fiordalice et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5602053 (1997-02-01), Zheng et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5653810 (1997-08-01), Kataoka et al.
patent: 5668055 (1997-09-01), Xu et al.
patent: 5702982 (1997-12-01), Lee et al.
patent: 5821620 (1998-10-01), Hong
patent: 5824599 (1998-10-01), Schacham-Diamand et al.
patent: 5869395 (1999-02-01), Yim
patent: 5956612 (1999-09-01), Elliott et al.
patent: 6069068 (2000-05-01), Rathore et al.
patent: 01-302842 (1989-12-01), None
Cao Phat X.
Micro)n Technology, Inc.
Workman & Nydegger & Seeley
LandOfFree
Utilization of energy absorbing layer to improve metal flow... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Utilization of energy absorbing layer to improve metal flow..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Utilization of energy absorbing layer to improve metal flow... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2927598