Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2001-06-22
2003-01-14
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S648000, C438S653000, C438S687000
Reexamination Certificate
active
06506668
ABSTRACT:
FIELD OF THE INVENTION
The invention herein described relates generally to the fabrication of conductive interconnects and the filling of vias in semiconductor chips. More particularly, the invention relates to a method of using copper to interconnect integrated circuit component parts in conjunction with a dielectric constant material used as a gap filler.
BACKGROUND OF THE INVENTION
The need for high performance semiconductor chips has continued to increase over the past several years. As the demand for better performance and faster semiconductor chips increases, so does the effort to reduce the size of semiconductor chips. Reducing the size of individual integrated circuit component parts can dramatically increase the speed and performance of a semiconductor chip. For example, smaller gate lengths in MOS transistors dramatically increases the switching speed of MOS transistors. The performance of semiconductor chips is limited by the electrical conductivity of the metal interconnects which electrically connect the various component parts that are contained in integrated circuits on the semiconductor chip. Therefore, in order to take full advantage of transistors capable of operating at faster speeds the electrical interconnects must be highly conductive, yet low in resistance.
In prior art metallization processes, aluminum or an aluminum alloy, was widely used as the preferred metallization metal. Metallization is the term used in the semiconductor industry to generally describe the process of “wiring” the component parts of an integrated circuit together. Aluminum emerged as the preferred metal for metallization because it has a relatively low resistivity (2.7 &mgr;&OHgr;/cm), a good current-carrying density, superior adhesion to silicon dioxide qualities, is available in high purity and has a natural low contact resistance with silicon. However, aluminum and aluminum alloys suffer from eutectic formations, thermally induced voiding and electromigration when used in very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor chips.
Copper metal has begun to replace aluminum and aluminum-silicon alloys in VLSI and ULSI metallization because it has better conductivity and is more reliable than other metals, such as aluminum and aluminum alloys. The use of electroplating techniques for performing metallization using copper is especially appealing because of low cost, high throughput, high quality of the deposited copper film and excellent via filling capabilities. Although aluminum has a resistance that can be tolerated by most integrated circuits, it is difficult to deposit in a high aspect ratio. Copper is capable of being deposited with high aspect ratios. Copper is also a much better conductor than aluminum, provides good step coverage, is more resistant to electromigration and can be deposited at low temperatures. However, copper will still diffuse into silicon if applied directly to the silicon without first applying a barrier layer between the silicon layer and the copper layer.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines that interconnect the component parts of the integrated circuit. Dual damascene is a multi-level interconnection process in which via openings are formed in addition to forming the grooves of single damascene. Conductive lines are then deposited that interconnect the active and passive elements of the integrated circuit contained on the semiconductor chip.
A current method of forming a copper interconnect consist of the steps shown in
FIGS. 1-6
. Referring to
FIG. 1
, a cross-sectional view of a portion of a semiconductor chip
100
is illustrated which includes a substrate layer
102
and an overlying dielectric layer
104
. As known in the art, the semiconductor chip
100
at this particular stage of manufacturing may include a variety of integrated circuit component parts that were formed during previously completed fabrication steps. The dielectric layer
104
is deposited on the surface of the substrate layer
102
using methods known in the art, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), spin on depositing or by thermal oxidation. The dielectric layer
104
can be selected from a variety of dielectric materials known to those in the art.
Next, as is illustrated in
FIG. 2
, the dielectric layer
104
is patterned using techniques known in the art to yield a patterned dielectric layer having patterned dielectric features
104
a
and openings
106
. As is illustrated in
FIG. 3
, once the dielectric layer
104
has been deposited and patterned accordingly, a barrier layer
108
is deposited on the patterned dielectric layer
104
a.
Materials used for the barrier layer
108
may be selected from several materials known in the art for providing a sufficient barrier between the substrate layer
102
and the metal deposited during the metallization process. The barrier layer
108
is deposited on the semiconductor chip
100
using several deposition techniques known in the art such as evaporation, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), ion-metal plasma (IMP), hollow cathode magnetron (HCM) or sputter ion plating (SIP).
The next layer deposited on the semiconductor chip
100
is a copper seed layer
110
. Like the barrier layer
108
, the copper seed layer
110
may be deposited on the semiconductor chip
100
using deposition techniques known in the art such as evaporation, IMP, CVD, PVD, HCM, SIP or PECVD. After the deposition of both the barrier layer
108
and the copper seed layer
110
, a copper layer
112
is electrodeposited by electroplating so as to over fill the openings
106
as illustrated in FIG.
4
. This entire structure is then subjected to annealing, as known in the art, in a nitrogen (N
2
) or forming gas atmosphere to yield a semiconductor
100
having an annealed layer
114
as illustrated in FIG.
5
. Finally, as is illustrated in
FIG. 6
, the excess copper of annealed layer
114
and the excess barrier layer
108
is remove to a suitable depth so as to yield copper interconnects
114
a
bound by the barrier layers
108
a.
The removal of the excess copper of layer
114
and the barrier layer
108
can be accomplished by any suitable method such as chemical mechanical polishing (CMP).
Although the above method generally yields suitable interconnects, the method suffers from one or more of the following shortcomings. First, post plating annealing leads to copper grain growth. Such grain growth is associated with copper volume changes which in turn can lead to void formation when a volume change occurs within a confined metal feature. Second, during the above-mentioned method it is difficult to control and/or improve copper texture. Third, the above-mentioned method makes it difficult to control the stress value of and/or relieve the stress in a copper layer.
Accordingly, a need exists in the semiconductor industry for methods of reducing electromigration in semiconductor devices. In addition, a need exists for a method of which permits the deposition of a copper conductive layer with a low stress value, a strongly face-centered cubic <111> oriented copper lines and via structures, and an improved copper texture. Also, a method is needed which allows for control or modification of the stress value and/or copper texture in a copper conductive layer. This is because strong texture and low stress copper improves reliability. Whereas good copper texture helps to slow copper migration through grain boundaries. Additionally, low stress also retards the onset of void formation.
SUMMARY OF THE INVENTION
The present invention relates generally to the fabrication of conductive interconnects and the filling of vias in semiconductor chips. More particularly, the invention relates to a method of using copper to interconnect integrated circuit component parts in conjunctio
Avanzino Steve C.
Mei-Chu Woo Christy
Wang Connie Pin-Chin
Advanced Micro Devices , Inc.
Lebentritt Michael S.
Renner , Otto, Boisselle & Sklar, LLP
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