Using negative gate erase voltage to simultaneously erase...

Details Using negative gate erase voltage to simultaneously erase... Using negative gate erase voltage to simultaneously erase...

2000-09-07

2002-03-12

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185180

Reexamination Certificate

active

06356482

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a non-volatile memory, and more particularly, to a method of performing an erase operation on a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure.
BACKGROUND ART
Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A variety of non-volatile memory devices with oxide-nitride-oxide (ONO) structures have been developed. An example of a typical non-volatile memory cell with an ONO structure includes a semiconductor substrate with source and drain regions, an oxide-nitride-oxide (ONO) film on top of the substrate surface between the source and the drain, and nitride layer on top of the first oxide layer, and a second oxide layer on top of the nitride layer. The nitride layer of the ONO film is capable of trapping electrons which are generated in the channel region of the semiconductor substrate during a programming operation.
The conventional non-volatile memory cell with a typical ONO structure is programmed by generating hot electrons in the vicinity of the drain region in the substrate and injecting the hot electrons into the ONO film. The hot electrons are trapped in a portion of the nitride layer close to the drain of the non-volatile memory cell. Because the nitride layer is an insulator, the hot electrons tend to remain in the portion of the nitride layer close to the drain without dispersing into other portions such as the center of the nitride layer.
The presence of negative charge in the portion of the nitride layer adjacent the drain indicates that at least the drain side of the non-volatile memory cell is in a “programmed” state. The non-volatile memory cell with a typical ONO structure may be programmed by applying high positive voltages to the gate and the drain, and grounding the source to inject hot electrons into the portion of the nitride layer adjacent the drain. An example of typical gate and drain voltages applied during programming are V
G
=9.0V and V
D
=4.0V. The program technique described is called channel hot electron programming.
A programming procedure may also be applied to inject hot electrons into the nitride layer of a cell close to the source. To provide electrons in the nitride layer near the source, a positive gate and source voltage are applied while the drain is grounded.
FIG. 1
shows a cross-sectional view of a non-volatile memory cell
2
which comprises a substrate
4
, an oxide-nitride-oxide (ONO) film
6
including a first oxide layer
8
on top of the substrate
4
, a nitride layer
10
of top of the first oxide layer
8
, and a second oxide layer
12
on top of the nitride layer
10
. A polysilicon gate
14
is provided on top of the second outside layer
12
. Portions of the substrate
4
are doped with a group V element, such as arsenic, to form a source region
16
and a drain region
18
. The source and drain regions
16
and
18
may be produced by implanting arsenic into the substrate
4
to a depth in the range of about 300 Å to about 600 Å. The ONO film
6
is positioned on top of a surface of the substrate
4
between the source
16
and the drain
18
.
The first oxide layer
8
, which is also called a tunnel oxide layer, is positioned directly on top of the surface portion
20
of the substrate
4
between the source
16
and the drain
18
. A channel exists in the substrate
4
beneath the first oxide layer
8
between the source
16
and drain
18
. The first oxide layer
8
may have a thickness on the order of about 75 Å.
The nitride layer
10
, which is positioned on top of the first oxide layer
8
, is capable of trapping hot electrons which are generated in the channel and injected into a portion
34
of the nitride layer
10
close to the drain region
18
during a typical programming operation. The nitride layer
10
may have a thickness on the order of about 75 Å. The second oxide layer
12
, which is positioned on top of the nitride layer
10
, has a thickness typically on the order of about 100 Å. The gate
14
, which is positioned on top of the second oxide layer
12
, may be a conventional polysilicon gate which serves as a control gate for the non-volatile memory cell. The ONO film
6
, which comprises the first oxide layer
8
, the second oxide layer
12
and the nitride layer
10
sandwiched between the first and second oxide layers
8
and
12
, may be fabricated by using conventional techniques known to a person skilled in the art.
FIG. 1
further shows portions of cross-sectional views of additional memory cells
22
and
24
adjacent the memory cell
2
in a non-volatile memory array. The non-volatile memory cells
22
and
24
each have a device structure identical to the non-volatile memory cell
2
described above. Furthermore, two adjacent non-volatile memory cells share a common arsenic-doped region which serves both as the drain for one of the cells and as the source for the other cell. For example, the arsenic-doped region
16
, which serves as the source for the non-volatile memory cell
2
, also serves as the drain for the non-volatile memory cell
22
. Similarly, the arsenic-doped region
18
, which serves as the drain for the non-volatile memory cell
2
, also serves as the source for the non-volatile memory cell
24
. The drain regions
16
and
18
are buried beneath oxide regions
15
and
17
used to isolate individual cells.
FIG. 2
shows a typical electron charge distribution in the substrate
4
after a typical programming operation in which channel hot electrons are generated in the substrate
4
and then trapped in the nitride layer
10
near the drain
18
. When the non-volatile memory cell
2
is programmed by applying a high gate and drain voltage while grounding the source, negative charge
32
is stored in the nitride layer
10
and is localized in the area
34
near the drain
18
. The hot electrons are trapped in the localized area
34
of the nitride layer
10
and remain localized without spreading or dispersing into other regions since the nitride layer
10
is an insulator.
FIG. 3
illustrates the distribution of electrons when the non-volatile memory cell
2
is programmed by applying a high source and gate voltage while grounding the drain. As shown, by programming with a high source voltage, negative charge
32
is stored in the nitride layer
10
and is localized in the area
36
near the source. The hot electrons are trapped in the localized area
36
and remain localized without spreading or dispersing.
A single cell can be programmed using the programming procedure where a high drain and gate voltage is applied while the source is grounded, as well as the procedure where a high source and gate voltage is applied while the drain is grounded. After both procedures are applied, electrons will be distributed in the nitride layer
10
in both localized regions
34
and
36
, as shown in FIG.
4
. As further illustrated in
FIG. 4
, the center of the nitride layer
10
tends to be free of electrons, and the electron distribution does not significantly disperse.
To read the programmed state of the cell programmed, as shown in
FIG. 2
, in a first (normal) procedure, a positive gate voltage is applied along with a positive source voltage while the drain is grounded. With the cell programmed, a greater threshold voltage V
T
will be created, so a greater gate to source voltage must be applied for the cell to conduct during read. With a higher threshold voltage, for the same read voltage applied, less source to drain current will flow.
A second (complementary) read procedure can be applied with the cell programmed as shown in
FIG. 2
which uses a positive gate voltage applied along with a positive drain voltage and the source grounded. With the electrons stored near the drain in region
34
, using the complementary read procedure the cell will not significantly change in threshold, unlike when the normal procedure is applied. Thus, using the complementary

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