Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-02-15
2003-04-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180
Reexamination Certificate
active
06549457
ABSTRACT:
BACKGROUND
This invention relates to semiconductor memories and particularly to multi-level cell memories.
A multi-level cell memory is comprised of multi-level cells, each of which is able to store multiple charge states or levels. Each of the charge states is associated with a memory element bit pattern.
A flash electrically erasable programmable read only memory (EEPROM) memory cell, as well as other types of memory cells, is configurable to store multiple threshold levels (V
T
). In the memory cell capable of storing two bits per cell, for example, four threshold levels (V
T
) are used. The bits are assigned values for each of the threshold levels.
In one embodiment, a multi-level cell may store four charge states. Level three maintains a higher charge than level two, level two maintains a higher charge than level one, and level one maintains a higher charge than level zero. Reference voltages may separate the various charge states. For example, a first reference voltage may separate level three and level two, a second reference voltage may separate level two from level one, and a third reference voltage may separate level one from level zero.
A multi-level cell memory is able to store more than one bit of data based on the number of charge states. For example, a multi-level cell memory that can store four charge states can store two bits of data, a multi-level cell memory that can store eight charge states can store three bits of data, and a multi-level cell memory that can store sixteen charge states can store four bits of data. For each of the N-bit multi-level cell memories, various memory element bit patterns may be associated with each of the different charge states.
The number of charge states storable in a multi-level cell, however, is not limited to powers of two. For example, a multi-level cell memory with three charge states stores 1.5 bits of data. When this multi-level cell is combined with additional decoding logic and coupled to a second similar multi-level cell, three bits of data are provided as the output of the two cell combination. Various other multi-cell combinations are possible as well.
In a single bit per cell memory, a single bit may be utilized as a status bit to determine whether the cell was programmed when a programming or write operation was interrupted by a power failure. With multi-level cell memories, more transitions are possible when programming the cell since there are more cell levels. As a result, a single bit status bit would be non-informing if a power failure occurred.
Thus, there is a need for a system which provides status information when a power failure occurs in connection with a multi-level memory write operation.
REFERENCES:
patent: 5774397 (1998-06-01), Endoh et al.
patent: 6163479 (2000-12-01), Chevallier
Dressler David S.
Fackenthal Richard E.
Rudelic John C.
Srinivasan Sujaya
Hoang Huan
Intel Corporation
Trop Pruner & Hu P.C.
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