Using clock gating or signal gating to partition a device...

Details Using clock gating or signal gating to partition a device... Using clock gating or signal gating to partition a device...

2005-03-08

2005-03-08

Raymond, Edward (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C711S173000

Reexamination Certificate

active

06865501

ABSTRACT:
In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

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C.J. Richard Shi, “Block-Level Fault Isolation Using Partition Theory and Logic Minimization Techniques” Mar. 1997, ECE Department, University of Iowa, Iowa City Iowa 52242, USA.

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