Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-08-15
2003-12-30
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S025000
Reexamination Certificate
active
06671644
ABSTRACT:
FIELD OF THE INVENTION
This invention is related to electronic devices including computer system chips, and in particular is concerned with improved diagnosis and isolation of faults in such devices.
BACKGROUND OF THE INVENTION
An earlier related patent application discloses clock gating in the context of a computer system chip with LBIST (logic built in self test) capability. This prior application is commonly assigned with the present application, has an inventor in common herewith, and issued on Sep. 26, 2000 as U.S. Pat. No. 6,125,465, entitled “Isolation/Removal of Faults during LBIST Testing”. The '465 patent is incorporated herein by reference in its entirety. The '465 patent discloses a diagnostic regime under which a clock signal is withheld from a functional unit of a chip which is known to have caused a fault. The remainder of the chip then can be tested to determine if there are further faults in the chip.
The present inventors have recognized that additional testing regimes can be employed using clock gating and/or signal gating.
SUMMARY OF THE INVENTION
According to an aspect of the invention, a method of testing an electronic device includes partitioning the device into segments by using clock gating or signal gating, and identifying one of the segments that is a source of a failure by selectively disabling at least one of the segments. The identifying of the failing segment may include enabling the segments one-by-one (with the other segments disabled) and applying a test to the enabled segment. Alternatively, the identifying of the failing segment may include disabling the segments one-by-one (with the other segments enabled) while applying a test to the device as a whole.
According to another aspect of the invention, a method of testing an electronic device includes partitioning the device into segments by using clock gating or signal gating, identifying one of the segments that is a source of a failure, and applying a diagnostic procedure to the identified segment to determine a cause of the failure. All of the segments may be logically independent of each other, or two or more of the segments may overlap each other. Numerous other aspects also are provided.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description with reference to the following drawings.
REFERENCES:
patent: 4509008 (1985-04-01), DasGupta et al.
patent: 4800564 (1989-01-01), DeFazio et al.
patent: 5119378 (1992-06-01), Welles, II et al.
patent: 5132974 (1992-07-01), Rosales
patent: 6125465 (2000-09-01), McNamara et al.
patent: 6536024 (2003-03-01), Hathaway
C.J. Richard Shi, “Block-Level Fault Isolation Using Partition Theory and Logic Minimization Techniques ” Mar. 1997, ECE Department, University of Iowa, Iowa City, Iowa 52242, USA.
Huisman Leendert M.
Huott William V.
Motika Franco
Pastel Leah M. Pfeifer
Dugan & Dugan
Hoff Marc S.
Raymond Edward
Walsh Robert A.
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