Thermal measuring and testing – Temperature measurement – By electrical or magnetic heat sensor
Reexamination Certificate
1999-12-02
2001-07-10
Gutierrez, Diego (Department: 2859)
Thermal measuring and testing
Temperature measurement
By electrical or magnetic heat sensor
C338S025000
Reexamination Certificate
active
06257760
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to determining the temperature of a semiconductor fabrication process by forming a resistivity versus temperature calibration curve for a superlattice structure having layers of a conductor interposed between layers of a semiconductor.
2. Description of the Relevant Art
Various processes are involved in the manufacture of a multi-level semiconductor device. Controlling the temperature of several of those processes is necessary to ensure that the resulting integrated circuit is operable and meets design specifications. Well known semiconductor fabrication processes which may require strict control of the processing temperature include, but are not limited to high density plasma deposition, high density plasma etching, plasma enhanced chemical vapor deposition (“PECVD”), low pressure chemical vapor deposition (“LPCVD”) reactive ion etching (“RIE”), various sputter deposition techniques, rapid thermal processing (“RTP”), and furnace annealing. For example, chemical vapor deposition processes and etching processes involve reacting species upon a surface of a semiconductor topography to either form a film or vaporize surface material. Deposition rate and etch rate are dependent upon the reaction rate of those surface reactions, and the reaction rate varies with temperature.
It is particularly critical for the temperature lobe uniform across a semiconductor topography during high density plasma deposition etching. Variations in temperature across a semiconductor topography may result in a non-uniform deposition or etch across the wafer. A film deposited using a high density plasma may, e.g., vary in thickness and stoichiometry across the wafer. A high density plasma may be generated using different types of reaction chambers. A high density plasma contains a relatively high concentration of ions (e.g., more hand approximately 10
12
ions/cm
3
) and excited atoms. One common feature of conventional high density plasma (“HDP”) reactors is the independent control over the generation of high density ions and ion energy. One type of high density plasma reactor is the inductively coupled plasma reactor. The plasma in such a reactor is created inside a vacuum chamber by a coiled radio frequency (“RF”) antenna. By adjusting the RF current in the antenna, the ion density can be controlled. The ion energy is controlled by another RF power connected to the platform upon which the wafer resides during the deposition or etch
The measurement of the temperature of a semiconductor topography is thus of significant importance in the field of integrated circuit fabrication. Unfortunately, because of various process conditions, e.g., high vacuum and chemically reactive surroundings, direct measurement of the temperature of a wafer via calibrated platinum film resistances (i.e., thermocouples) and other contact thermometers is generally not possible. For example, ions and excited species created in a high density plasma are highly reactive and could possibly react with the thermocouples themselves. Further, variations in temperature across a wafer make direct measurement of the wafer temperature even more difficult Multiple thermocouples must be placed in contact with various regions of the wafer during the processing. Moreover, the temperature at one location on the wafer may change over the course of the process, reducing the precision of the temperature measurement at that location. As such, determining the exact temperature of the critical point of a process, e.g., the temperature at which species diffuse to and react upon a topological surface, appears desirable, yet conventionally impossible.
It would therefore be of benefit to develop a method for determining a precise and accurate temperature of a semiconductor topography during the critical part of a fabrication process. Further, it would be desirable to avoid using temperature measurement devices, e.g., thermocouples, which could interact with species during the fabrication process. A method is needed which would allow the process temperature to be determined prior to actually subjecting a semiconductor topography to the fabrication process. Once an accurate measurement of the process temperature is attainable, it would be possible to strictly control the temperature of a semiconductor topography during a fabrication process. The temperature controls could be adjusted in order to approach the targeted process temperature. Eventually the targeted process temperature could be reached across each temperature position of the topography, and as a result, the outcome of the fabrication process would be significantly advanced. Consequently, an integrated circuit which operates according to design could be fabricated.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the technique hereof for determining the temperature of a semiconductor fabrication process by forming a resistivity versus temperature calibration curve for a superlattice structure. A similar superlattice structure may then be subjected to the temperature at which the critical portion of the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure subjected to processing ambient, the calibration curve may be used to determine the process temperature of the superlattice structure during the critical portion of the fabrication process. The length of time that the superlattice structure is subjected to the process temperature is selected to be the time duration of the process whose temperature is being determined.
Once the actual process temperature is known, the temperature controls for the process may be adjusted in an attempt to reach the desired process temperature. The technique hereof may be repeated until the desired process temperature is equivalent to the actual process temperature. After calibration of the process temperature, the semiconductor fabrication process may be performed upon a semiconductor topography at the desired process temperature. In this manner, the process temperature of the semiconductor topography may be determined without directly measuring the semiconductor topography temperature. As a result, the process temperature may be strictly controlled, making it possible to achieve the desired outcome of a semiconductor fabrication process. For example, the temperature of an HDP deposition process may be controlled to provide for the desired deposition rate and stoichiometry of the film being deposited.
In an embodiment, a superlattice structure is first formed upon a silicon-based substrate. Alternating thin layers, i.e., sublattices, of a conductor and a semiconductor may be, e.g., sputter deposited across the substrate from targets bearing the conductor and the semiconductor. The sublattices are deposited at a relatively low temperature, i.e., less than about 25° C., to minimize the interdiffusion between the sublattices, thereby forming well-defined interfaces between the sublattices. The conductor and the semiconductor chosen for the superlattice depends upon the type of semiconductor process being analyzed. For a low temperature process, such as an HDP process, a superlattice structure comprising alternating layers of aluminum and silicon may be formed since the melting point of aluminum is between 600° C. and 700° C. and an HDP process is typically performed at a temperature of 200° C. to 400° C. Since the process temperature of an RTP process typically ranges from 600° C. to 1,000° C., the superlattice structure may comprise alternating layers of titanium and titanium silicide which have relatively high melting points. Conductors which may be appropriate for use in the superlattice include, but are not limited to, aluminum, copper, titanium, and tungsten., Semiconductors which may be appropriate for use in the superlattice structure include, but are not limited to
Davis Bradley M.
Song Shengnian Davis
Sun Sey-Ping
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Gonzalez Madeline
Gutierrez Diego
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