Electrical computers and digital processing systems: processing – Byte-word rearranging – bit-field insertion or extraction,...
Reexamination Certificate
2005-07-28
2008-12-09
Huisman, David J (Department: 2183)
Electrical computers and digital processing systems: processing
Byte-word rearranging, bit-field insertion or extraction,...
Reexamination Certificate
active
07464255
ABSTRACT:
A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The shuffle unit is adapted to support shift operations as well. In response to determining a shuffle instruction is received, selected bits of an immediate value of the shuffle instruction are used to generate byte selects for relocating bytes of a source operand. In response to determining the instruction is a shift instruction, the shuffle unit performs an arithmetic operation on a first and second value, where the first value corresponds to a particular destination byte position, and the second value corresponds to the immediate value. The result of the arithmetic operation comprises a byte select which selects one of the bytes of a source operand for conveyance to the particular destination byte position. In the event a destination byte position should be cleared by the shift operation, the output for the particular destination byte position is forced to zero.
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U.S. Appl. No. 11/197,705, filed Aug. 4, 2005.
Goveas Kelvin Domnic
Tan Teik-Chung
Advanced Micro Devices , Inc.
Huisman David J
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Rankin Rory D.
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