Using a low drain bias during erase verify to ensure...

Details Using a low drain bias during erase verify to ensure... Using a low drain bias during erase verify to ensure...

2000-10-04

2002-12-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185260, C365S185290, C365S185300

Reexamination Certificate

active

06501681

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a non-volatile memory, and more particularly, to a method of performing an erase-verify operation on a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure.
BACKGROUND
Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A variety of non-volatile memory devices with oxide-nitride-oxide (ONO) structures have been developed. An example of a typical non-volatile memory cell with an ONO structure comprises a semiconductor substrate with source and drain regions, a channel region which is formed close to the surface of the semiconductor substrate between the source and the drain when electrical conduction occurs between the source and the drain, an oxide-nitride-oxide (ONO) film on top of the substrate surface between the source and the drain, and a gate on top of the ONO film. The ONO film comprises three layers including a first oxide layer on top of the substrate surface between the source and the drain, a nitride layer on top of the first oxide layer, and a second oxide layer on top of the nitride layer. The nitride layer in the ONO film is capable of trapping electrons which are generated in the channel region of the semiconductor substrate during a programming operation.
The conventional non-volatile memory cell with a typical ONO structure is programmed by generating hot electrons in the vicinity of the drain region in the substrate and injecting the hot electrons into the ONO film. More specifically, the hot electrons are trapped in a portion of the nitride layer close to the drain of the non-volatile memory cell. Because the nitride layer is an insulator, the hot electrons tend to remain in the portion of the nitride layer close to the drain without dispersing into other portions such as the center of the nitride layer.
The presence of the trapped hot electrons in the portion of the nitride layer adjacent the drain signifies that at least the drain side of the non-volatile memory cell is “programmed”. The non-volatile memory cell with a typical ONO structure may be programmed by applying high positive voltages to the gate and the drain and grounding the source of the non-volatile memory cell to inject hot electrons into the portion of the nitride layer adjacent the drain. This technique is also called channel hot electron programming.
FIG. 1
shows a cross-sectional view of a non-volatile memory cell
2
which comprises a substrate
4
, an oxide-nitride-oxide (ONO) film
6
comprising a first oxide layer
8
on top of the substrate
4
, a nitride layer
10
of top of the first oxide layer
8
, and a second oxide layer
12
on top of the nitride layer
10
. A polysilicon gate
14
is provided on top of the second outside layer
12
. Portions of the substrate
4
are doped with a group V element, such as arsenic, to form a source region
16
and a drain region
18
. The source and drain regions
16
and
18
may be produced by implanting arsenic into the substrate
4
to a depth in the range of about 300 Å to about 600 Å. The ONO film
6
is positioned on top of a surface portion
20
of the substrate
4
between the source
16
and the drain
18
.
The first oxide layer
8
, which is also called a tunnel oxide layer, is positioned directly on top of the surface portion
20
of the substrate
4
between the source
16
and the drain
18
. When conduction occurs between the source
16
and the drain
18
, a channel is formed in the substrate
4
close to the surface
20
between the source
16
and the drain
18
. The first oxide layer
8
may have a thickness on the order of about 75 Å.
The nitride layer
10
, which is positioned on top of the first nitride layer
8
, is capable of trapping hot electrons which are generated in the channel and injected into a portion
34
of the nitride layer
10
close to the drain region
18
during a typical programming operation. The nitride layer
10
may have a thickness on the order of about 75 Å. The second oxide layer
12
, which is positioned on top of the nitride layer
10
, has a thickness typically on the order of about 100 Å. The gate
14
, which is positioned on top of the second oxide layer
12
, may be a conventional polysilicon gate which serves as a control gate for the non-volatile memory cell. The ONO film
6
, which comprises the first oxide layer
8
, the second oxide layer
12
and the nitride layer
10
sandwiched between the first and second oxide layers
8
and
12
, may be fabricated by using conventional techniques known to a person skilled in the art.
FIG. 1
further shows portions of cross-sectional views of additional memory cells
22
and
24
adjacent the memory cell
2
in a non-volatile memory array. The nonvolatile memory cells
22
and
24
each have a device structure identical to the non-volatile memory cell
2
described above. Furthermore, two adjacent nonvolatile memory cells share a common arsenic-doped region which serves both as the drain for one of the cells and as the source for the other cell. For example, the arsenic-doped region
16
, which serves as the source for the non-volatile memory cell
2
, also serves as the drain for the non-volatile memory cell
22
. Similarly, the arsenic-doped region
18
, which serves as the drain for the non-volatile memory cell
2
, also serves as the source for the non-volatile memory cell
24
.
FIG. 1
shows a typical electron charge distribution in the substrate
4
after a typical programming operation in which channel hot electrons are generated in the substrate
4
and then trapped in the nitride layer
10
. Such a programming operation is also called channel hot electron programming. After the non-volatile memory cell
2
is programmed, negative charge is formed in the portion of the substrate
4
beneath the substrate surface
20
between the source
16
and the drain
18
. Electrons are trapped in this substrate region during the channel hot electron programming operation with an electron charge distribution in dependence upon the gate and drain voltages applied to the non-volatile memory cell
2
during the programming operation and the doping profiles for the source region
16
and the drain region
18
.
More specifically,
FIG. 1
shows an example of a typical electron charge distribution
26
in the portion of the substrate
4
between the source
16
and the drain
18
of the non-volatile memory cell
2
in which both the drain side and the source side are programmed. The negative charge in the substrate
4
is relatively concentrated in a first region
28
adjacent the source
16
and in a second region
30
adjacent the drain
18
after a typical channel hot electron programming operation. Furthermore, hot electrons are injected into the nitride layer
10
of the ONO film
6
during the programming operation.
Since the nitride layer
10
is an insulation layer, hot electrons which are trapped in the nitride layer
10
tend to remain localized within certain regions of the nitride layer
10
without spreading or dispersing into other regions of the nitride layer
10
. In the example shown in
FIG. 1
in which both the drain side and the source side are programmed, hot electrons
32
are trapped in a first portion
34
of the nitride layer
10
adjacent the drain
18
and a second portion
36
of the nitride layer
10
adjacent the source
16
. Furthermore, as shown in
FIG. 1
, the center of the nitride layer
10
tends to be free of hot electrons, and the electron charge distribution in the substrate
4
tends to be minimal in the center region between the source
16
and the drain
18
.
Depending upon the manner in which the nonvolatile memory cell
2
is programmed, electron charge distributions in the substrate
4
and the nitride layer
10
may be different from those shown in FIG.
1
. For example, if only the drain side of the non-volatile memory cell
2
is programmed with hot electrons, only the portion
34
of the nitride layer

Affiliated with

Also associated with

Rating

Using a low drain bias during erase verify to ensure... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Using a low drain bias during erase verify to ensure..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using a low drain bias during erase verify to ensure... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2977648