Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2001-12-20
2003-12-09
Snow, Walter E. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S691000, C324S719000
Reexamination Certificate
active
06661242
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an automated test equipment (ATE) system for testing integrated circuit devices, a corresponding device under test (DUT), and the channel path between these two elements. More specifically, the present invention relates to the accurate determination of the resistance of the channel path between the ATE system and the DUT, and the compensation of subsequent test results in view of this determined channel path resistance.
DESCRIPTION OF RELATED ART
FIG. 1
is a schematic diagram of a channel path of a conventional test system
100
including a device under test (DUT)
101
, a test system interface board
102
and an automated test equipment (ATE) system
103
. ATE system
103
includes PIN electronics
104
and a board precision measurement unit (BPMU)
105
. Resistances R
1
-R
6
extend along the channel path between DUT
101
and the voltage measuring point of BPMU
105
. Resistance R
1
represents the resistance between DUT
101
and the DUT socket. Resistance R
2
represents the resistance between the socket and test system interface board
102
at the end of the channel path near DUT
101
. Resistance R
3
represents the resistance of a circuit trace on test system interface board
102
. Resistance R
4
represents the resistance between test system interface board
102
and the PIN electronics at the end of the channel path near ATE system
103
. Resistance R
5
represents the resistance of PIN electronics
104
. Resistance R
6
represents the output series resistance of BPMU
105
.
Channel path resistance (R
CHAN
) is defined as the total series resistance from the ATE system
103
to DUT
101
. Stated another way, the channel path resistance R
CHAN
is the sum of all the component resistances in the measurement path. Thus, in the example of
FIG. 1
, the channel path resistance R
CHAN
is equal to R
1
+R
2
+R
3
+R
4
+R
5
+R
6
. Previously, there has been no accurate method for directly monitoring the channel path resistance R
CHAN
while ATE system
103
is performing a test on DUT
101
. One reason for this is unknown measurement system error present in test system
100
. However, it would be useful to be able to monitor changes in the channel path resistance R
CHAN
due to changes in any or all components of the channel path resistance R
CHAN
. If the actual channel path resistance R
CHAN
were known, it would be possible to determine whether DUT
101
has erroneously failed a test because of the channel path resistance R
CHAN
.
SUMMARY
Accordingly, the present invention provides a novel method for monitoring ATE channel path resistance R
CHAN
during testing. The method is useful for maximizing yields of semiconductors with marginal DC output levels. The present invention can be implemented in all ATE measurement environments requiring accurate path resistance determination and compensation. The present invention advantageously provides an increase in product yield, dependent on the product's tolerance of the path resistance. That is, the yield increase will be greater for products with less tolerance to path resistance.
In an embodiment of the present invention, resistance values within the ATE system (i.e., R
5
and R
6
) are known parameters. However, the contact resistance between the device under test and the ATE system (i.e., R
1
+R
2
+R
3
+R
4
) is not a known parameter. The contact resistance must therefore be determined in order to determine the channel resistance R
CHAN
.
In one embodiment, a method of determining a contact resistance between an automated test equipment (ATE) system and a device under test (DUT) includes the following steps. The DUT is configured to drive a predetermined voltage to a pin of the DUT. The ATE system is then controlled to force a first (known) test current into the DUT. After the first test current has been established, the board precision measurement unit BPMU of the ATE system measures a first voltage provided by the ATE system to force the first test current.
The ATE system is then controlled to force a second test current to flow out of the DUT. The ATE system controls the second test current to have the same magnitude as the first test current (even though the first and second test currents flow in opposite directions). After the second test current has been established, the BPMU of the ATE system measures a second voltage provided by the ATE system to force the second test current.
The channel resistance is then determined in response to the measured first voltage, the measured second voltage and the magnitude of the first (or second) test current.
In a particular embodiment, the internal resistance of the ATE system is also used to determine the channel resistance. For example, the channel resistance may be determined by subtracting the second voltage from the first voltage, dividing the result by twice the magnitude of the first test current and subtracting the internal resistance of the ATE system from the result. Such a calculation effectively cancels any voltage measurement errors inherent in the ATE system.
In one embodiment, the magnitude of the first (and second) test current is selected to be large enough that a difference between the first voltage and the second voltage is large enough to be detectable. In accordance with another embodiment, the magnitude of the first (and second) test current is selected to be small enough that the predetermined voltage of the DUT is not affected by the first and second test currents. To accomplish this, the magnitude of the first (and second) test current can be selected to be at least an order of magnitude smaller than a rated current output of the DUT at the predetermined voltage.
REFERENCES:
patent: 5554928 (1996-09-01), Stringer
patent: 6331783 (2001-12-01), Hauptman
Hoffman E. Eric
Nguyen Vincent Q.
Snow Walter E.
Xilinx , Inc.
Young Edel M.
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