User transparent self-calibration technique for pipelined...

Details User transparent self-calibration technique for pipelined... User transparent self-calibration technique for pipelined...

1999-02-01

2001-02-06

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000

Reexamination Certificate

active

06184809

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to self-calibration of pipelined analog-to-digital converters.
Analog to Digital Conversion
Analog to digital conversion is the process of converting an analog data signal, which is most commonly represented as voltage, into a digital format. Determining a digital value which represents a particular analog input is known as “quantization”. Serial, delta-sigma or oversampling, parallel, and pipelined are some of the many different analog to digital conversion architectures which exist. Different architectures are suited to different needs.
Serial analog to digital architecture offers the widest range of performance in analog to digital conversion, from low power and low resolution to quantizations with very high resolutions. Basic serial architecture quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution will take N cycles to fully quantize. Delta-sigma analog to digital architecture is used in audio signal processing. The architecture is designed to translate high-speed, low-resolution samples into higher-resolution, lower-speed output. This process is also referred to as oversampling because more samples of the analog data are quantized than actually become output. Parallel analog to digital architecture provides the fastest quantization rate per analog signal. In the parallel architecture, a digital value per cycle is produced for each analog data sample, without regard to N, the number of bits of resolution. Parallel architecture requires that all quantization levels be simultaneously compared to the analog signal. This results in the use of 2
N−1
comparators and 2
N−1
resistors to achieve a digital value, with N bits of resolution, per cycle.
Pipelined Analog-to Digital Architecture
Pipelined analog to digital architecture is a method of quantizing an analog signal in stages. Algorithms exist for obtaining one or more bits of resolution per stage. For example, in a 1.5-bit per stage converter, the digital output of each stage is either 1, 0, or −1. One bit is resolved at each stage with the resulting analog residue passed along to the next stage for resolution of another bit. After a latency of N cycles, a single digital value for a single analog input is produced. Other methods are able to output more than 1 bit per stage, needing fewer latency cycles to produce a digital value with the same resolution. The use of pipelining permits a high degree of parallelism, so that one complete output per cycle can be produced after the pipeline fills up.
Pipelined analog to digital converters have many applications. They are particularly useful when low voltage, high speed, high resolution quantization is required. The pipelined analog to digital conversion architecture's ability to meet these demands makes it ideal for high volume telecommunications application such as various digital subscriber lines, digital signal processing at video rates, and for stand alone high speed analog to digital converters.
The advantage of pipelined analog to digital conversion is that each stage of resolution is separated. Once the analog signal is resolved at the first stage and the result passed to the second stage, a new signal can be processed by the first stage. The passing of result and signal from stage to stage continues to stage N at which point a digital value of N bits of resolution can be produced. Quantization of the first signal to N bits of resolution is achieved in N cycles of latency. However, because each stage resolves one bit and passes the result to the next stage, the former stage is free to resolve a bit of the next analog sample.
This pipeline design allows N analog samples to be in the process of quantization simultaneously. Once the first analog sample is quantized, after N cycles, each successive analog sample is quantized one cycle later. Thus, a high throughput of one sample per cycle is achieved.
Analog to Digital Conversion Error
Errors can be introduced into the conversion process at different stages by different components. The most common components in analog to digital conversion which can cause error are capacitors. Capacitors can introduce error because of a mismatch concerning the capacitance ratio of two or more capacitors used in sampling and amplifying an analog signal.
Capacitor Mismatch and Non-Linearity
A digital self-calibration technique for pipelined analog to digital converters which corrects for capacitor mismatch has been disclosed in Hae-Seung Lee, A 12-B 600
KS/S
D
IGITALLY
S
ELF
-C
ALIBRATED
P
IPELINED
A
LGORITHMIC
ADC, IEEE Journal of Solid State Circuits, Vol 29, No. 4, Apr. 1994, at 509, which is incorporated herein by reference. This article demonstrates the necessary steps for determining the mismatch ratio of two nominally equal capacitors. The difference of the capacitance between two nominally equal capacitors, C
1
and C
2
, can be represented as C
1
=(1 +&agr;
i
)C
2
where &agr;
i
represents the mismatch ratio in capacitance between capacitors C
1
and C
2
. Once &agr;
i
is known, the error due to capacitance mismatch can be canceled by adding a digital correction quantity:
α
i
2
i
[
(
D
⁡
(
i
)
/
2
i
-
D
⁡
(
i
+
1
)
/
2
i
+
1
-
D
⁡
(
i
+
2
)
/
2
i
+
2
-
…
]
to the digital output, where D(i) represents the digital output of the ith stage of a pipelined analog to digital converter.
In the Lee article, several assumptions are made concerning the need for digital self-calibration and the extent to which error should be corrected. The article assumed that the only linearity error present in a 1.5 bits per stage converter is caused by capacitor mismatch. This assumption was based on the presence of an operational amplifier at each stage of the pipeline with “high enough” gain to effectively eliminate the amplifier gain and non-linearity. In other words, the article assumes an amplifier with infinite gain.
Analog ti Digital Background Calibration Techniques
Various self-calibration techniques have been proposed to address the capacitor mismatch induced by the digital to analog subconverter (DASC) and interstage gain error. Most of these techniques require the normal operation of the converters to be interrupted in order to perform the calibration. This can impose a burden on the user who must decide when the converter can be interrupted and when the converter needs be re-calibrated due to temperature or other environmental changes. A superior method is to use a background calibration technique whose operation is transparent to the user. Three different background calibration techniques have recently been proposed.
Measuring Error with a &Sgr;-&Dgr; Analog to Digital Converter (ADC)
An approach using a &Sgr;-&Dgr; analog-to-digital converter (or “ADC”) to measure the DASC error is given by Tzi-Hsiung Shu, A 13
-B
10-M
SAMPLE/S
ADC D
IGITALLY
C
ALIBRATED WITH
O
VERSAMPLING
D
ELTA
-S
IGMA
C
ONVERTER
, IEEE Journal of Solid State Circuits, Vol 30, No. 4, April 1995, at 443, which is incorporated herein by reference. In this approach, once the error is measured, it is subtracted out in the digital domain. The drawback of this technique is that it requires the DASC to be implemented as a resistor string which dissipates DC current. The reason for using a resistor string is that the DASC analog output levels are continuously available. This availability makes continuous calibration simple to implement at the expense of power consumption. Another drawback of this technique is that the added &Sgr;-&Dgr; ADC consumes power and area. Furthermore, any interstage gain error present in the ADC is not calibrated. The use of a resistor string digital to analog converter (DAC) highlights the difficulty of user-transparent calibration with a capacitor DAC.
Measuring Error Using an Extra Clock Cycle
Another background calibration technique which allows the ADC to occasionally skip one clock cycle to permit the calibration to be performed is given by Sung-Ung Kwak,

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