Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-02-25
2002-07-23
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185240
Reexamination Certificate
active
06424569
ABSTRACT:
BACKGROUND
A flash cell can be a field effect transistor (FET) including a select gate, a floating gate, a drain, and a source. A cell can be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to select gate, the cell can be switched on and off.
Flash memory cells can be grouped into NAND type and NOR type circuits. NAND flash memory cells have an n cell transistors connected in series and are connected in parallel between bit lines and ground lines. NAND flash memory cells are useful in large scale integration. NOR flash memory cells include cell transistors that are connected in parallel between bit lines and ground lines. NOR flash memory cells provide high-speed operation.
Programming a cell includes trapping excess electrons in the floating gate to increase voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The memory cell is programmed when the cell current is less than a reference current and the select voltage is applied. The cell is erased when the cell current is greater than the reference current and the select voltage is applied.
Memory cells with only two programmable states contain only a single bit of information, such as a “0” or a “1”.
A multi-level cell (“MLC”) is a cell that can be programmed with more than one voltage level. Each voltage level is mapped to corresponding bits of information. For example, a multi-level cell can be programmed with one of four voltage levels, −2.5V, 0.0V, +1.0V, +2.0V that correspond to binary “00”, “01”, “10”, and “11”, respectively. A cell that is programmable at more voltage levels can store more bits of data based on the following equation:
N=
2
{circumflex over ( )}B Eqn. 1
B is the number of bits of data stored
N is the number of voltage levels.
The amount of data stored in a cell can be increased by using more than two programming states. Thus, two or more bits of data are stored in each cell. A cell with four states requires three threshold levels. U.S. Pat. Nos. 5,043,940 and 5,172,338 described such cells and are incorporated herein by this reference.
More time is required to program a cell with more states to avoid overshooting a desired smaller programming range. To insure that the cell is programmed properly, the cell is programmed beyond the threshold level. This technique tends to increase the programming time since the required programming accuracy is increased.
FIG. 1
shows a representation of a four level multilevel cell program voltage diagram
100
. The program voltage distribution (“distribution”) of the four levels are shown between lines
102
and
104
,
106
and
108
, lines
110
and
112
, and above line
114
, respectively. The programming distribution can be for example 100 mV to 600 mV wide. A four level multilevel memory cell can be programmed with any one of these voltage levels. Because the cell can store one of four binary values it can store 2 bits of information. The data margin (“margin”), also called a guard band, is the voltage levels between distributions that is not normally used. The margins are shown in
FIG. 1
between lines
104
and
106
; lines
108
and
110
; and lines
112
and
114
. For example, the data margin can be 800 mV to 100 mV wide.
FIG. 2
shows the affect of the phenomena called “read disturb.” Read disturb occurs after the cell has been read many times without being reprogrammed. The programming distributions are shifted to the right, which represents a positive voltage shift. Distributions
230
,
232
,
234
, and
236
represent the distributions
220
,
222
,
224
, and
226
after they have been affected by the read disturb. Eventually, the read disturb can become so severe that the stored data becomes unreliable, such as at lines
210
and
212
.
FIG. 3
shows the affect of the phenomena called “data retention.” Data retention causes the distributions
220
,
222
,
224
, and
226
to be shifted to the left as shown by distributions
320
,
322
,
324
, and
326
, which represents a negative voltage shift. Over time if the cell is not reprogrammed, the data retention shift can cause the stored data to become unreliable.
BRIEF SUMMARY OF THE PREFERRED EMBODIMENTS
A user selectable option is added to a memory cell, such as a multilevel NAND flash cell, that allows the user to select whether to optimize programming time or the data integrity.
A mode selection mechanism can switch the programming mode of each cell. A first programming mode programs the cell with a first programming voltage and maintains at least fifty percent of the maximum data margin. A second programming mode programs the cell with a second programming voltage and maintains at least eighty five percent of the maximum data margin. The first programming voltage is greater than the second programming voltage.
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Parker Allan
Skrovan Joseph
Advanced Micro Devices , Inc.
Zarabian A.
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