User-proof post-assembly offset voltage trim

Details User-proof post-assembly offset voltage trim User-proof post-assembly offset voltage trim

1990-08-21

1992-01-07

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including differential amplifier

330307, H03F 345

Patent

active

050795163

ABSTRACT:
A post-assembly trim of a monolithic IC is set forth wherein selected package pins can be employed to address the on-chip trim circuit. Then, after the trim is completed, the circuit is addressed to provide a disconnect of the coupling between the trim pins and the post assembly trim circuit of the IC, while leaving the pins fully usable for other purposes. This means that following the post-assembly trim the trim pins cannot accidentally be employed for further trimming and the packaged IC is user-proof. A circuit that employs zener zapping for both trimming and disconnect is detailed and the invention is clearly usable for plastic encapsulated devices. However, when cavity containing packages are involved it is shown that a combination of zener zapping and fuse blowing can be employed.

REFERENCES:
patent: 4481478 (1984-11-01), Flink et al.
patent: 4851786 (1989-07-01), Vinn et al.

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