Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2000-03-22
2001-10-02
Hjerpe, Richard (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S011000, C712S016000, C709S200000, C709S209000
Reexamination Certificate
active
06298430
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to user-configurable multiprocessor computational systems having ultra-scalar single-type computational logic.
Developing new computational processor systems for continuously changing application requirements has a primary architectural problem of tradeoff between user selectivity for high specialization efficiency and general-purpose use with lower efficiency. General-purpose processors like the well-known Pentium, PowerPC and Alpha can perform any algorithm that is programmed adequately for using their respectively generalized instruction sets. They can not obtain the performance efficiency, accuracy and speed of application-specific integrated circuits (ASIC) that are developed for specific applications and which implement only the functions that are required to run a dedicated specific task. ASIC structure having computational algorithm generally adequate for a particular application task can be small, less expensive and yet faster than a general-purpose programmable microprocessor. For example, a special graphic module for a PC can accelerate a process of drawing graphical primitives ten-to-twenty times the process speed of a general-purpose processor, but is efficient for one specific computational task only. Any alteration of the task or its conditions makes the ASIC totally useless.
It is not economically feasible to develop ASICs for a vastness of range of applications that is increasing continuously. The conventional solution for achieving ASIC advantages is to construct electronically huge general-purpose microprocessors that have pluralities of separate computational units which can be programmed by a computer manufacturer to function like a specialized ASIC. Each separate conventional computational unit is an oversized, slow and expensive general-purpose microprocessor that is known as a field-programmable gate array (FPGA).
In conventional FPGA architecture, manufacturers construct dedicated smallness efficiency from general-purpose largeness inefficiency. A huge manufacturer-specialized FPGA becomes an ASIC-substitute FPGA that requires massive chip silicon to achieve genuine small ASIC objectives. In addition to orders of magnitude of excess silicon, there is comparable waste of in-and-out computational time with ASIC-substitute FPGAs.
By contrast with this invention, instead of requiring massive excesses of computer-chip silicon and time lag for each of many manufacturer-specialized ASIC-substitute FPGAs, a dynamically reconfigurable microprocessor has been described by the present inventor in a prior patent application having Ser. No. 09/088,165, filed Jun. 1, 1998. In addition to that invention, this invention by the same inventor provides architecture and computational method for further speeding and adapting computer processing.
With dynamic reconfiguration, a user instead of a manufacturer can configure and reconfigure one or a small plurality of microprocessors to accomplish what previously required large pluralities of manufacturer-configured FPGAs or many more ASICs.
Added to dynamic reconfiguration by this invention are higher computational speed, smaller-yet chip size, greater computational adaptivity, greater programmable adaptivity and more “computer-centric” adaptivity.
SUMMARY OF THE INVENTION
Objects of patentable novelty and utility taught by this invention are to provide a user-configurable ultra-scalar multiprocessor and method which:
increases computational speed, accuracy and reliability of user-configurable multiprocessors;
decreases mass, space and cost of computer-chip material required per multiprocessor capability;
decreases quantity of integrated circuits required per multiprocessor capability; and
increases ease, speed and convenience of configuring and reconfiguring multiprocessors by users and by computer instruction.
This invention accomplishes these and other objectives with a user-configurable ultra-scalar multiprocessor having a predetermined plurality of distributed configurable signal processors (DCSPs) which each have at least two processing elements which are sub microprocessors (SMs) and one packet bus controller (PBC) that are a unit group. The DCSPs, the SMs and the PBC are connected through local network buses. The PBC has communication buses that connect the PBC with each of the SMs. The communication buses of the PBC that connect the PBC with each SM has serial chains of one hardwired connection and one programmably switchable connector. Each communication bus between the SMs is at least one hardwired connection and two programmably switchable connectors.
Dynamic reconfiguration can be termed user configuration (UC) or integrated-circuit (IC) configuration with architecture that will be referred to herein as a distributed configurable signal processor (DCSP). A DCSP consists of a set of identical processing elements, each of which are a sub microprocessor (SM). Different from an FPGA which is manufacturer programmable, each SM has its own microprogram control. A plurality of SMs can be combined programmably into separate SM groups which operate as specialized processors that can be application specific selectively. This allows the structures of each specialized processor to be adaptable optimally to an application algorithm. A plurality of SMs can be programmably combined into separate groups which operate as virtual and yet different application-specific or variously specialized processors. The architecture of an entire DCSP, therefore, can be configured, adapted and reconfigured to specific application tasks by a user and/or as programmed. This allows a previously impossible level of computer capability, task adaptation, speed and accuracy. When the application task or its conditions are altered, configuration of the DCSP can be altered easily and quickly by user reprogramming of its SM instead of being “field programmable” permanently by a computer manufacturer after being produced by a chip manufacturer of FPGAs.
Highly important in addition, DCSPs are hardware units that employ a new and much faster method for digital signal processing. This new method for digital signal processing is called ultra-scalar (US) processing.
For US processing, coordinated instruction codes for an application task having an input operand are directed to a plurality of SMs for each of the SMs to perform a separate data processing operation on different data digital groups of the input operand. The input operand is split into a plurality of parts that are processed by separate SMs. A designated “master” SM within the plurality of SMs performs a first directed operation on a first data digital group having a first preset plurality of preset high digits of the operand. Sequentially and similarly, one or more SMs designated as “slave” SMs within the plurality of SMs or within neighboring DCSPs
1
then performs a second directed operation on a second data digital group of the operand having a second preset plurality of preset low digits of the operand.
Result digits are obtained in the same order.
As a result digit is obtained from the preset high digits, computations with variable data length can be performed by breaking computations when a required accuracy is reached. Machine instruction is overlapped in time sequences in a manner not possible with conventional parallel computational processing which does not have adequate linkage of computational processing and information between computational processing of high digits and computational processing of low digits. This is an additional increase in computational power of the DCSPs.
In addition, architecture of DCSPs increases operational reliability considerably by proximate overlap implementation of regimes of both ultrareliable and fault-tolerant computations. The ultrareliable computations can be implemented by using a plurality of SMs for a predetermined instruction. Results from the plurality of SMs are compared and, if not the same, then repeated until appropriately similar results are obtained from each of the plurality of SMs. T
Context, Inc. of Delaware
Hjerpe Richard
Monestino Mackly
LandOfFree
User configurable ultra-scalar multiprocessor and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with User configurable ultra-scalar multiprocessor and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and User configurable ultra-scalar multiprocessor and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2603481