Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-11-17
2003-05-20
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C326S027000, C326S083000
Reexamination Certificate
active
06567773
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a process for noise analysis of integrated circuits, and in particular to a process for static noise analysis of an integrated circuit fabricated in a silicon-on-insulator (“SOI”) process technology.
2. Description of Related Art
Simulation-based static transistor-level analysis, both for noise and timing analysis, typically relies on fast circuit simulators such as ACES (an IBM internal simulator) or EPIC TIMEMILL (a product of Synopsis/EPIC). These simulators use a fixed set of models to represent the behavior of the transistors in the circuit, the model selection being done by the designer in the schematic. These fixed set of models do not allow the methods to take into account significant variation in the behavior of individual transistors in the circuit, whether due to process variation or (in the case of SOI) history effects.
Transistor-level analysis is popular for high performance designs, and technologies like SOI require that device variations be taken into account in such analysis. When significant variation exists in the behavior of individual transistors, a static analysis which is intended to ensure that specifications and functionality requirements are met, must take that variation into account. Variation in different transistors in a circuit can have different effects on the result being sought, i.e., having one transistor faster than average can increase noise, while having another faster than average can decrease noise. Therefore, methods which vary the behavior of all transistors in the network simultaneously, are inadequate.
Noise in integrated circuits can lead to functional failure of a circuit. Static analysis of noise in a circuit is a technique that analyzes the complete design in such a way that the entire design does not have to be simulated simultaneously at one time, which reduces the simulation time. Yet it guarantees that no failures will be missed.
This method of analysis is achieved by breaking each design into a set of subcircuits in such a way that the entire design is represented by a mathematical graph where the nodes of the graph represent the subcircuits, and the edges of the graph represent the nets or wire connections between the subcircuits. The graph is sorted, similar to levelization in static timing analysis, so that when any node is analyzed, all preceding circuits that could affect this node's inputs have previously been analyzed. Each subcircuit is analyzed completely in the presence of a variety of noise sources, with the results of the subcircuit simulations propagated to successor circuits in the larger design, using the sorted graph.
Analysis of each subcircuit for noise requires individual simulations of the subcircuit in the presence of various noise sources, to properly characterize the circuit's response to capacitive coupling noise, power supply variations, charge sharing within the subcircuit, and injected noise or noise coming from a preceding circuit to the inputs of the subcircuit. Injected noise analysis can also be extended to include a sensitivity analysis of the circuit, to characterize how the circuit will respond to the input noise and to understand how the output voltage of a circuit changes with respect to the input voltage changes caused by noise.
However, analysis of circuits fabricated in a partially depleted SOI process is further complicated by two effects, hysteresis and bipolar leakage.
Hysteresis is an effect in a circuit such that the behavior of the circuit depends on its state in the past, and can only be determined with the knowledge of the circuit's past behavior over a long period of time (many hundreds of switching cycles). Because the body nodes of SOI FETs are not explicitly tied to a power supply node, but rather left floating, the threshold voltage of the device varies in device operation and is conditional upon the body voltage. This varying threshold voltage changes the reaction of a circuit to normal and noisy input voltages. Thus knowing the voltage of all the terminals of a MOSFET in SOI technology, at any given moment in time, is not sufficient to predict its behavior in the future. The history of the voltage at those terminals is required in order to predict the behavior of the circuit. The noise analyses of the prior art do not take into account hysteresis, which limits the ability to effectively test and analyze integrated circuits fabricated in a SOI process technology.
Parasitic bipolar leakage is the current that can flow between the drain and source of an FET even when the gate is biased such that the FET is turned off In bulk CMOS technology, the parasitic bipolar exists, but the bipolar transistor is always off in normal device operation because the body in nFETs is grounded (or tied to Vdd for pFETs). This is not the case in SOI FETs, where the body node can be positively biased with respect to the source and may turn on the bipolar transistor. Significant current can flow between the source and drain of the transistor even when the gate is off, leading to noise on the circuit's output node, possibly causing functional failure of successor circuits. This effect is most important in dynamic circuits where the output voltage is determined by the voltage on a node which does not have a DC-path to the power supply voltage (VDD), but rather is determined by the capacitive charge on that node. Any leakage of that charge can produce a faulty output node value. The prior art does not intentionally set up conditions that will lead to bipolar leakage nor will it be modeled in a typical piecewise linear circuit simulator.
The prior art does not suggest simulations or models to account for the history effect, and using single-value body voltage models or floating body voltage models will not adequately simulate a worst case response to noise and could optimistically undercalculate a net's voltage deviation caused by noise.
Injected noise analysis of SOI circuits is not accurate unless both hysteresis and parasitic bipolar leakage current are taken into account during simulation. Similarly, a charge sharing simulation must take hysteresis and bipolar leakage into account to be accurate. Also, for the coupling noise calculation, the victim resistance used may depend on the threshold voltage of the victim FET and therefore, in the case of SOI, the use of fixed threshold voltage for all FET's would be correct.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method to analyze electrical noise in an integrated circuit fabricated in a SOI process technology.
It is another object of the present invention to provide a method of circuit analysis that accounts for the behavior of individual transistors in a circuit.
It is another object of the present invention to provide a method of circuit analysis that simulates the effects of hysteresis in an SOI circuit.
A further object of the invention is to provide a method of circuit analysis that simulates parasitic bipolar leakage current in an SOI circuit.
It is yet another object of the present invention to provide a method of analysis that simulates the behavior of individual transistors in an SOI circuit.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for analyzing electrical noise in an integrated circuit fabricated in a silicon-on-insulator process. In the preferred embodiment, the method comprises first describing an electrical circuit having at a least one transistor. At least one input voltage for the transistor is selected to precondition the circuit for a worse case response to electrical noise. In the preferred embodiment, the step of preconditioning th
Rahmat Khalid
Rose Ronald D.
DeLio & Peterson LLC
International Business Machines - Corporation
Makhdoom Samarina
Peterson Peter W.
Schnurmann H. Daniel
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