Abrading – Precision device or process - or with condition responsive... – By optical sensor
Reexamination Certificate
2002-10-22
2004-03-09
Shakeri, Hadi (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
By optical sensor
C451S005000, C451S041000, C451S287000
Reexamination Certificate
active
06702648
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to inspecting wafer surfaces during polishing for indications of delamination.
BACKGROUND ART
Many modem integrated circuits generally include multiple layers of metallic or conductive wiring surrounded and covered by insulating or dielectric layers. Maintaining the utmost accuracy in the deposition of these layers and subsequent formation of conductive and nonconductive features is critical in achieving smaller and smaller device dimensions and higher packing densities using conventional lithographic processes.
In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photoresist mask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photoresist mask causes a chemical transformation in the exposed areas of the coating thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
As the trend of decreasing the size of devices on chips and of increasing the size of a silicon die simultaneously continues, constant improvements are required in order to satisfy and exceed the demands of the marketplace. For example, in the area of interconnect structures, low dielectric constant (k) materials are beginning to replace higher dielectric constant materials due to the many benefits of low k materials. Since finer conductors are being placed ever closer together, lower k materials tend to be more desirable in order to minimize circuit impedance and decrease the on-chip power dissipation.
However, because lower k materials are typically weaker and more porous than their higher k counterparts, they may present problems during fabrication such as delamination or peeling of the thin film layers. Delamination may result from structural collapse of the film from excessive down-force, and from damage started by macroscratches.
Thus, there is an unmet need to detect for delamination in thin films in order to decrease device flaws and performance deficiencies and to increase overall product yield.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides for a system and method of examining a wafer during a polish process for delamination or indications thereof. In particular, the system and method involve detecting film delamination events occurring during chemical mechanical polishing (CMP) processing of interconnect structures. Furthermore, the present invention may be performed in real time, thus allowing for an immediate reaction or response by a user or by the polishing system/process to an occurrence of film delamination on the wafer.
This real time examination for delamination may be accomplished in part by employing a metrology system and one or more delamination sensors such that the metrology system, delamination sensors and the CMP system operate cooperatively with one another. For example, the metrology system includes light sensitive measuring instruments. A change in reflected light intensity may be indicative of a delaminated film area on the wafer. A change in scattered light intensities may be indicative of delamination within repetitive line patterns in a grating. The delamination sensors comprise optical elements to facilitate transmitting light directed to and reflected from the wafer. Because the delamination sensors are operatively connected to the metrology system, the data can be communicated from the sensors and to the metrology system. The metrology system may further process and/or analyze the data generated from the wafer in order to determine whether delamination has been detected.
The CMP system may be signaled to temporarily or permanently suspend itself until further instructions are transmitted thereto to indicate a resumption of polishing. Thus, the present invention provides for real time delamination examination and detection as well as a real time response to delamination. Furthermore, one or more polishing components may be adjusted according to the detected delamination. As a result, delamination on the wafer may be mitigated and/or repaired, and delamination may be mitigated with respect to future wafers and/or future polishing processes.
One aspect of the present invention relates to a system for real-time examination of delamination during a polishing process. The system includes a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system operatively coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors operatively connected to the polishing system and employed in conjunction with the polishing system, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the real time metrology system and wherein the sensor comprises at least one optical clement to detect delamination during polishing.
Another aspect of the present invention relates to a method for real-time examination of delamination during a polishing process. The method involves providing a wafer having one or more film layers formed thereon such that at least an uppermost film layer is prepared to be polished, the uppermost film layer being a copper layer; polishing at least the uppermost film layer; examining at least a portion of a film layer immediately underlying the uppermost layer for delamination as the uppermost layer is being polished; and determining whether to suspend the polishing process according to data generated from at least the immediately underlying film layer. In an alternative application, the low-k material might be present as a deeply underlying film layer, and the deeply underlying low-k material may be subject to delamination as the overlying film layers are polished.
Yet another aspect of the present invention relates to a system for real-time examination of delamination during a polishing process. The system includes a means for providing a wafer having one or more film layers formed thereon such that at least an uppermost film layer is prepared to be polished, the uppermost film layer being a low dielectric material; a means for polishing at least the uppermost film layer; a means for examining at least a portion of the uppermost film layer for delamination as it is being polished; and a means for determining whether to suspend the polishing process according to data generated from at least the uppermost film layer.
REFERENCES:
patent: 6204922 (2001-03-01), Chalmers
patent: 6476921 (2002-11-01), Saka et al.
patent: 6515493 (2003-02-01), Adams et al.
Avanzino Steven C.
Rangarajan Bharath
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Shakeri Hadi
LandOfFree
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