Use of polysilicon layer for local interconnect in a CMOS or BiC

Details Use of polysilicon layer for local interconnect in a CMOS or BiC Use of polysilicon layer for local interconnect in a CMOS or BiC

1990-07-24

1992-01-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 35, 437 56, 437 59, H01L 21265, H01L 21225

Patent

active

050827960

ABSTRACT:
A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BiCMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconnects. A conformal silicon dioxide layer is subsequently deposited and etched for forming oxide spacers on the sidewalls of the polysilicon layer. By selectively doping the polysilicon layer and exposed portions of the substrate, a continuous active region is formed beneath the polysilicon layer and the sidewall spacers.

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