Use of output impedance control to eliminate mastership change-o

Details Use of output impedance control to eliminate mastership change-o Use of output impedance control to eliminate mastership change-o

1991-08-14

1993-12-28

Kuntz, Curtis

Pulse or digital communications

Repeaters

Testing

370 851, 333 32, H04B 300

Patent

active

052746712

ABSTRACT:
An output resistance (R.sub.O) is situated at each output of a plurality of drivers communicating to a plurality of receivers via an interconnect network which is biased by a terminal supply voltage (V.sub.T). The output resistance R.sub.O eliminates the need for a wait period in a cycle, which wait period is usually required when mastership of the interconnect network changes over from one driver to another driver. The drivers and receivers are two-state devices. For a logic high, the drivers exhibit a virtually infinite resistance. Consequently, the interconnect network exhibits a high voltage V.sub.INT, which is approximately equal to the terminal supply voltage V.sub.T. Whereas for a logic low, the drivers sink current from the interconnect network, thereby pulling the interconnect network voltage V.sub.INT towards ground. Any signal below about (7/8)*V.sub.T is recognized by the receivers as a logic low, while any signal above this threshold is recognized as a logic high. In the case of a logic low, the voltage V.sub.INT is prevented from being pulled to ground by the output resistance (R.sub.O). The driver sinks enough current so that the voltage V.sub.INT is approximately equal to V.sub.T /2. Accordingly, if a change over occurs in a cycle after a logic low, the newly active driver can immediately drive a logic high or low onto the interconnect network, because the voltage V.sub.T /2 is readily available on the interconnect network. If the newly active driver wishes to drive a logic high, the driver exhibits infinite resistance, and the voltage V.sub.INT increases to V.sub.T. If the newly active driver wishes to drive a logic low, the driver sinks current, and the voltage V.sub.INT increases to only about (3/4)*(V.sub.T), which is recognized as a logic low. The voltage V.sub.INT will ultimately decrease to V.sub.T /2, thereby enhancing its disposition as a logic low.

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patent: 5046072 (1991-09-01), Shimizu et al.
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