Semiconductor device manufacturing: process – Repair or restoration
Reexamination Certificate
2000-08-01
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Repair or restoration
Reexamination Certificate
active
06372522
ABSTRACT:
TECHNICAL FIELD
The present invention pertains to the field of integrated circuit device fabrication. More particularly, the present invention relates to a system for improving the effective yield of an integrated circuit device fabrication process through the use of selective device repair.
BACKGROUND ART
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems obey the properties their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, mass producing the systems without flaws or defects becomes increasingly difficult. For example, for a given level of process technology, as the total number of transistors fabricated within an integrate circuit die increases and the area of each fabricated die increases, the total number of fully functional dies produced from each wafer (e.g., the yield) decreases, due to he increased chance of inadvertent manufacturing defects. In addition, the collective yield for a new process technology will usually be low, with the yield increasing as the process technology matures.
For example, commonly encountered manufacturing defects include “shorts”, or defects between conductive lines/elements within the IC. A short defect occurs when, for example, a contaminant particle (e.g., dust, etc.) causes extraneous metal deposit to occur across conductive lines or elements. The extraneous metal deposit electrically shorts the lines, disrupting the functionality that depends upon them. Other commonly encountered defects include “opens” that occur when, for example, a contaminant particle causes an inadvertent discontinuity during the deposition of one or more metal lines. The inadvertent discontinuity disrupts the functionality that depends upon the one or more lines.
Thus, any integrated circuit devices including defects such as shorts or opens are most likely defective, and must be discarded. Very sophisticated test programs, automatic test pattern generation (ATPG) programs, are used to analyze the various netlists representative of the integrated circuit designs. The ATPG process is designed to facilitate the detection of defective integrated circuit devices. An integrated circuit device is defective if it includes one or more defects, or flaws within its internal circuitry, which interfere with its proper functionality. The most advanced manufacturing processes produce large numbers of defective devices along with nominal devices. A typical yield for an advanced manufacturing process is, for example, 70 percent, wherein 70 percent of the fabricated devices are nominal and 30 percent of them are defective. Only the nominally performing, defect free integrated circuit devices are shipped to customers.
The problem, however, is the fact that complex integrated circuit devices are usually very expensive to fabricate. The more advanced the process technology and the larger the die, the more expensive the completed integrated circuits become. The lower the yield, the more expensive the fully functional devices become. Hence, very desirable to adjust the process to maintain as high a yield as possible. Accordingly, high performance integrated circuit device fabrication is one of the most precise and exacting manufacturing processes in existence.
The costs associated with discarding defective integrated circuit devices is prohibitive. Because of this, complex repair processes have been developed. These repair processes actually correct the defect (e.g., short, open, etc.) which impairs the functionality of the device. After a defective integrated circuit emerges from the wafer fabrication process, the nature of the defect is identified and the defect is repaired to restore functionality, thus, increasing the total yield of the manufacturing process and reducing the costs associated with each fully functional device.
Consequently, the selective repair (formation and disconnection) of interconnect links, metal lines, and the like, after the completion of wafer processing is finding rapid acceptance in certain high density applications. Such applications include, for example, high density (e.g., 1 Gb) DRAM, SRAM, logic with embedded memory, “system on a chip”, smart cards, and analog and mixed signal applications.
Laser repair is one technique utilized. Laser repair involves using laser energy on a localized area (e.g., an area exposed through passivation layers) to selectively “blow” certain predetermined links. The goal of this technique, for example, is to electrically isolate the defect site. However, certain integrated circuit parameters (e.g., the thickness of the oxide layer at the localized area) can make the effectiveness of the laser energy unpredictable. For example, varying thickness of the oxide layer can modulate the effective absorption of the laser energy by the localized area, rendering the performance of laser repair somewhat variable and unreliable.
Thus, what is required is a system that yields predictable and efficient performance of selective repair of interconnect links. What is required is a system that is less susceptible to integrated circuit parameters such as oxide thickness. The present invention provides a novel solution to the above requirements.
DISCLOSURE OF THE INVENTION
The present invention provides a system that yields predictable and efficient performance of selective repair of interconnect links. Additionally, the present invention provides an interconnect repair method and system that is less susceptible to integrated circuit parameters such as oxide thickness.
In one embodiment, the present invention is implemented as a system of repairable interconnect links built into a semiconductor integrated circuit die. The repairable interconnect links are configured and optimized to facilitate repair through the use of laser energy applied to specific areas of the surface of the semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. To repair a specific defect occurring within the die (e.g., a bad memory cell due to a flaw), a specific interconnect link included in the integrated circuit die is identified. This interconnect link is selected such that the selective repair (e.g., fusing) of the link effects, for example, an isolation of the fault from the rest of the circuit, or for example, the linking in of a backup element(e.g., memory cell) to replace the faulty element.
The selected repairable interconnect link typically couples first and second interconnect elements of the integrated circuit. At the surface of the die, an anti-reflective layer is disposed above the interconnect link. The anti-reflective layer is deposited over the link during the wafer fabrication process (e.g., “just-in-case” the link needed to be fused). The anti-reflective layer is configured to increase an amount of laser energy absorbed by the interconnect link. Correspondingly, this decreases the amount of laser energy needed to be applied in order to ensure the fusing of the interconnect link. These aspects render the repair process using laser energy more deterministic and predictable, thereby improving the success rate and the overall yield of the fabrication process, and thereby repair the integrated circuit die. Additionally, the repair process is less susceptible to integrated circuit parameters such as oxide thickness above or below the interconnect link.
REFERENCES:
patent: 5545904 (1996-08-01), Orbach
patent: 5600165 (1997-02-01), Tsukamoto et al.
patent: 6061264 (2000-05-01), Giust et al.
Patent Abstracts of Japan vol. 007, No. 103 (E-173), May 6, 1983—& JP 58 023475 A ( Fujitsu KK), Feb, 12, 1983 abstract.
Bothra Subhas
Sethi Satyendra
Weling Milind Ganesh
Berry Renee R.
Nelms David
VLSI Technology Inc.
Wagner , Murabito & Hao LLP
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