Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-06-29
2003-06-10
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S536000, C257S760000, C257S904000, C257S379000, C257S381000, C438S381000, C438S954000
Reexamination Certificate
active
06576978
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor processing and specifically to the use of silicon oxynitride films as resistive elements.
BACKGROUND OF THE INVENTION
The four transistor (4-T) SRAM cell, shown schematically in
FIG. 1
, is a well known architecture that is often preferred over its 6-T counterpart due to its small cell size. The 4-T architecture uses two access transistors T
1
and T
2
and two storage transistors T
3
and T
4
that are cross-coupled in a traditional flip-flop-type fashion. This architecture also uses two load resistors R
1
and R
2
to limit the current draw through the cell. These resistors are usually of a very high resistance (on the order of Giga-ohms/square) and optimally limit the current draw through the cell to a value of about 30-35 pA.
The load resistors are typically fabricated in a second layer of polysilicon (poly 2) and this well-known fabrication process is briefly described here. After formation of the gates of the four transistors in poly 1, an interpoly dielectric, usually a silicon dioxide or “oxide” for short, is deposited and two contacts per cell are etched therein. These two contacts correspond to points A and B on the circuit schematic of FIG.
1
and each contact is generally made to expose both a portion of the gate of one of the storage transistors and a portion of the diffusion region (i.e., source or drain) of the other storage transistor and one of the access transistors. For example, the contact at point A exposes the gate of storage transistor T
3
and one of the diffusion regions of storage transistor T
2
and access transistor T
4
. Thereafter, the poly 2 is deposited. This poly 2 is usually doped with a suitable n-type dopant (usually phosphorus) in situ during its deposition, although it may also be doped after deposition. Thereafter, a portion of the poly 2 is masked to expose the location of the load resistors. These exposed portions of the poly 2 are then subjected to p-type doping (usually arsenic), and then the poly 2 is patterned and etched. The effect is to make an n-p-n structure in the poly 2, a structure which comprises two back-to-back diodes and thus draws the very low levels of current that are required for suitable operation of the cell. See Wolff & Tauber, Silicon Processing for the VLSI Era, Vol. 2 Process Integration, ch. 8, pg. 582 for more background concerning the processing and architecture of a typical 4-T SRAM cell.
Other attempts have been made to fabricate the load resistors not out of polysilicon, but out of a dielectric material. Thus, in U.S. Pat. No. 5,616,951 to Liang, there is disclosed a vertical resistor
28
inside of the contact
27
in the interpoly oxide
24
. The resistor is comprised of an oxide-nitride-oxide stack, an oxide-nitride stack, or a nitride-oxide stack (see FIG.
8
). Liang's resistor is in contact with both the poly 1 gates
26
and the poly 2
25
to thus achieve a 4-T SRAM cell of suitable functionality. However, the fabrication process for Liang's resistor is complicated and involves the deposition or growth of numerous layers. In U.S. Pat. No. 4,950,620 to Harrington, there is disclosed a process for making a load resistor out of the gate oxide by ion implanting it with arsenic. Harrington also discloses that silicon oxynitrides (“oxynitrides”) or silicon nitrides (“nitrides”) may also be used. Unfortunately, Harrington's process requires this extra ion implantation step to render the gate dielectric resistive enough to function properly as a load resistor. U.S. Pat. No. 5,200,356 to Tanaka is similar to Harrington's process in that it involves the ion implantation of silicon or phosphorous into the gate dielectric to manufacture the load resistor. These prior art references are hereby incorporated by reference in their entirety for all that they teach.
It is evident from foregoing descriptions that the prior art takes several processing steps to form the load resistors. Moreover, it has proven difficult to shrink or scale SRAM cells that employ poly 2 load resistors. It would be advantageous to instead use a film in lieu of the poly 2 of suitable resistance such that that film could merely be deposited and patterned without additional processing such as ion implantation, and which could be easily scaled for use in future technologies.
SUMMARY OF THE INVENTION
In view of the foregoing considerations, the present invention is directed to the use of non-ion-implanted resistive silicon oxynitride films as resistive elements. Such films have been traditionally used in semiconductor processing as antireflective coatings, but their utility as highly resistive circuit elements has heretofore not been realized. Such films find specific utility when used as the load resistors in a 4-T SRAM cell.
REFERENCES:
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patent: 5200356 (1993-04-01), Tanaka
patent: 5616951 (1997-04-01), Liang
patent: 5930638 (1999-07-01), Reedy et al.
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patent: 6124198 (2000-09-01), Moslehi
patent: 6127238 (2000-10-01), Liao et al.
patent: 6209484 (2001-04-01), Huang et al.
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patent: 2001/0006842 (2001-07-01), Hattori
patent: 61172754 (1986-08-01), None
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patent: 62201264 (1987-09-01), None
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Toshiyuki Okumura et al., “A SiOx Resistor Load SRAM Process for ASIC Applications”, IEEE, 1998 Custom Integrated Circuits Conference, 1998, pp. 25.6.1-25.6.4.*
Wolf, “Silicon Processing for the VLSI Era, vol. 2” (pp. 274-275).
Díaz José R.
Howrey Simon Arnold & White , LLP
Lee Eddie
LandOfFree
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