Use of low-high slurry flow to eliminate copper line damages

Details Use of low-high slurry flow to eliminate copper line damages Use of low-high slurry flow to eliminate copper line damages

1999-05-03

2003-07-08

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S690000, C438S693000, C438S007000, C438S008000, C438S720000

Reexamination Certificate

active

06589872

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the field of the fabrication of semiconductor devices, and more specifically to a method of performing Chemical Mechanical Polishing of copper lines in a damascene structure by using-a unique slurry flow.
(2) Description of the Prior Art
The present invention relates to the creation of conductive lines and vias that provide the interconnection of integrated circuits in semiconductor devices and/or the interconnections in a multilayer substrate on which semiconductor device(s) are mounted. The present invention specifically relates to the fabrication of conductive lines and vias by a process known as damascene.
Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
The increasing need to form planar surfaces in semiconductor device fabrication has led to the development of a process technology known as Chemical Mechanical Planarization (CMP). In the CMP process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
U.S. Pat. No. 5,451,551 teaches that, in the evolution of integrated circuit chips, scaling down feature sizes makes device performance more heavily dependent on the interconnections between devices. In addition, the area required to route the interconnect lines becomes large relative to the area occupied by the devices. This normally leads to integrated circuit chips with multilevel interconnect schemes. The chips are often mounted on multi-chip modules that contain buried wiring patterns to conduct electrical signals between the various chips. These modules usually contain multiple layers of interconnect metalization separated by alternating layers of an isolating dielectric. Any conductor material to be used in a multilevel interconnect has to satisfy certain essential requirements such as low resistivity, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical) and ease of processing.
Copper is often preferred due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper unfortunately suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
The copper must also be patterned. Photolithography is a common approach wherein patterned layers are usually formed by spinning on a layer of photoresist, projecting light through a photomask with the desired pattern onto the photoresist to expose the photoresist to the pattern, developing the photoresist, washing off the undeveloped photoresist, and plasma etching to clean out the areas where the photoresist has been washed away. The exposed resist may be rendered insoluble (positive working) and form the pattern, or insoluble (negative working) and be washed away. In either case, the remaining resist on the surface forms the desired pattern. Photoresist, however, not only consumes time and resources but also endangers contamination from particulates and etchant solutions. Dry etches may also be employed in copper patterning processes employing masks. However, dry etches tend to be resisted by copper. In addition, dry etches are expensive due to the high Capitol cost reaction ion etch (RIE) systems and are limited in application because they require a hard mask such as nickel, aluminum or gold. Thus, a method of patterning copper without photolithography or dry etching is desirable. Regardless of the conductor material or patterning techniques planarization of the interlayer dielectric is crucial for obtaining a multilevel structure that allows accurate lithographic patterning. The deposition and etchback tolerances associated with large film thickness are cumulative, and any non-planarity of the resist is replicated in the final top surface of the device. Chemical-mechanical polishing is a fast and efficient approach for achieving planarity in multichip modules and integrated circuits.
FIG. 1
shows a Prior Art CMP apparatus. A polishing pad
20
is affixed to a circular polishing table
22
that rotates in a direction indicated by arrow
24
at a rate in the order of 1 to 100 RPM. A wafer carrier
26
is used to hold wafer
18
face down against the polishing pad
20
. The wafer
18
is held in place by applying a vacuum to the backside of the wafer (not shown). The wafer
18
can also be attached to the wafer carrier
26
by the application of a substrate attachment film (not shown) to the lower surface of the wafer carrier
26
. The wafer carrier
26
also rotates as indicated by arrow
32
, usually in the same direction as the polishing table
22
, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table
22
, the wafer
18
traverses a circular polishing path over the polishing pad
20
. A force
28
is also applied in the downward vertical direction against wafer
18
and presses the wafer
18
against the polishing pad
20
as it is being polished. The force
28
is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft
30
that is attached to the back of wafer carrier
26
.
A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles.
Abrasive interaction between the

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