Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2003-01-21
2004-09-21
Flynn, Nathan J (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C438S626000, C438S631000, C438S692000, C438S697000
Reexamination Certificate
active
06794691
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to semiconductor device fabrication technology, and more specifically, to structures and methods for placing irregularly shaped metal filler features in a layer of a multiple layer circuit to improve planarization of the layer while reducing parasitic capacitance introduced by the filler metal.
2. Background and Related Art
Computing technology has revolutionized the way people work and play and has contributed enormously to the advancement of humankind. Much of computing technology has been enabled by the discovery and advancement of semiconductor processing technology.
Semiconductor processing technology allows for the formation of highly integrated circuits with multiple metal layers. The minimum feature size within these fabricated circuits has been declining and now is well below one micron (commonly 0.18 or 0.13 microns). For a sense of scale, one micron is just one thousandth of a millimeter. Accordingly, extremely complex and powerful circuits can be fabricated all within a relatively small space. This allows electronic circuits to be relatively unobtrusive while yet providing significant technological achievement in even small devices such as mobile telephones.
As previously mentioned, such integrated circuits are often fabricated with multiple metal layers. Each metal layer includes a patterned metal material (such as Aluminum). An appropriate insulating layer (such as Silicon Dioxide) is formed over the patterned metal material. Each metal layer is most reliably fabricated when the surface upon which the metal layer is formed is relatively flat. Accordingly, once the fabrication of a metal layer has been completed by the formation of the insulating material over the metal, and if there are to be further metal layers formed thereon, the insulating material is planarized so that the yet-to-be-fabricated upper metal layers may have a smooth foundation upon which to be fabricated. Typically, such planarization is accomplished using a high-precision Chemical-Mechanical Polish (CMP) machine that uses a combination of mechanical force and chemical reaction to planarized the surface.
One conventional and known problem associated with planarization is illustrated in
FIGS. 3A and 3B
.
FIG. 3A
illustrates a vertical cross-section
300
A that includes a metal layer covered with insulating material prior to planarization. A metal material
301
is formed on a relatively flat substrate
302
. For example, the metal material
301
may be a metal wire in which case the metal wire may extend into and out of FIG.
3
A. The substrate
302
may be composed of a crystalline semiconductor or other material, or may be the planarized insulator of a lower metal layer. An intermetallic insulation material
303
is deposited over the metal
301
to avoid shorting the metal material
301
with any metal in the yet-to-be-fabricated upper metal layers. Note that the insulation material crests upward at about the position of the metal material as labeled by arrow
304
. On the other hand, the insulation material ebbs fairly low at other positions far away from the metal material as labeled by arrow
305
.
FIG. 3B
illustrates a cross section
300
B of the fabricated metal material with surrounding insulation material after planarization. Note that some portions of the insulation material have been properly planarized (e.g., the portion above and close by the metal material). However, due to the ebbing of the insulation material, some portions of the insulation material have remained relatively unaffected by the planarization. This results in the occurrence of topological recessions called “dishes” within what was hoped to be a relatively flat top surface of the metal layer. For example, surface
306
over the metal material
301
is relatively flat, while surface
305
remains recessed and largely unaffected by planarization.
In order to guard against this dishing and enable better planarization, it is common to place dummy metal filler features in spaces between active metal. For example, in the cross section
300
A of
FIG. 3A
, a designer may opt to place filler metal features on the substrate
302
at about the position of the arrow
305
to thereby reduce ebbing that would appear alter the insulation is formed. Accordingly, dishing would be eliminated or at least less pronounced.
Although the active and filler metal are physically isolated, there is some capacitive interaction. For example, the filler metal has some capacitive coupling to the active metal in both the same metal layer as well as the active metal in other metal layers. This capacitive coupling has the effect of slowing down the operation of the circuit as a whole. Despite such performance degradation, metal is typically used as the filler material. due to processing efficiencies since the filler metal can be formed with the same processing steps as are used to form the active metal assuming an appropriately patterned mask.
FIG. 4
illustrates a conventional layout as viewed downwards perpendicular to the plane defined by the substrate (hereinafter referred to as a “topview”). The active metal regions (i.e., the metal that forms part of the operating integrated circuit) are defined by those regions such as region
401
that are filled with diagonal hatch lines. The filler metal regions are defined by those regions such as region
402
that are filled with dots. Each discrete rectangular filler region corresponds to a metal filler feature.
The capacitive coupling of the filler metal with upper and lower active metal material is a strong function of the layout area occupied by the metal filler regions. Also, the capacitive coupling of the metal filler features with the active metal within the same metal layer is a function of the size of the end of the metal filler feature that is closest to the active metal. As seen from
FIG. 4
, there is a large amount of layout area consumed by the rectangular metal filler features. Also, the size of the most proximate edge of the metal filler feature that is closest to the active metal may be quite large depending on the orientation of the active metal since the filler features are rectangular. Accordingly, there is some capacitive coupling caused by the introduction of the filler metal.
What would be advantageous would be mechanisms for using metal filler features in a manner that reduces such capacitive coupling.
BRIEF SUMMARY OF THE INVENTION
The foregoing problems with the prior state of the art are overcome by the principles of the present invention, which are directed towards an integrated circuit (and a corresponding method of fabricating the same) in which there is a number of conductive layers (e.g., metal or highly-doped polycrystalline semiconductor). At least one of the conductive layers has irregularly shaped and properly spaced conductive filler features. In particular, the conductive layer includes a number of active conductive components that are used for the electrical operation of the integrated circuit. Also, conductive filler features are interposed amongst the active conductive components.
Each of the conductive filler features may be conceptually bounded by a bounding box that has upper, right, lower, and left edges that aligns with the upper-most, right-most, lower-most, and left-most edges, respectively, of the corresponding conductive filler feature. At least some and potentially all of the conductive features are spaced from each other so that the bounding box of each of the conductive filler features does not overlap with any other bounding box of any of the other conductive filler features. In addition, the conductive filler features occupy only a fraction (perhaps from approximately fifteen to seventy percent, or perhaps from approximately twenty-five to fifty-five percent) of its bounding box. By spacing in this manner, the capacitive coupling with the active conductive components in the upper and/or lower conductive layers may be reduced.
The conductive features may be,
AMI Semiconductor Inc.
Flynn Nathan J
Greene Pershelle
Workman Nydegger
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