Use of indium to define work function of p-type doped...

Details Use of indium to define work function of p-type doped... Use of indium to define work function of p-type doped...

2003-01-03

2004-10-12

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S250000, C257S285000, C257S357000

Reexamination Certificate

active

06803611

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor processing, and more particularly to a methodology for isolating a silicon dioxide, silicon oxynitride or high-k gate dielectric from a p-type dopant such as boron added to an overlying gate electrode in a PMOS transistor.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward manufacturing integrated circuits (ICs) with a greater number of layers and with higher device densities. To achieve these high densities there have been, and continues to be, efforts towards reducing the thickness of layers, improving the uniformity of layers, reducing the thickness of devices and scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish such higher device packing densities, thinner layers, more uniform layers, smaller feature sizes, and smaller separations between features are required. This can include the thickness of gate dielectric materials (e.g., SiO
2
), the width and spacing of interconnecting lines, the spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance, and can lead to higher effective yield in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer. Such advantages are a driving force to constantly scale down IC dimensions.
The process of manufacturing integrated circuits typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. Generally, the process involves creating several layers on and in a substrate that ultimately forms the complete integrated circuit. This layering process can create electrically active regions in and on the semiconductor wafer surface. In MOS transistors, for example, a gate structure is created, which can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor. The source and drain regions facilitate this conductance by virtue of containing a majority of p or n type materials. The regions are typically formed by adding dopants to targeted areas on either side of the channel region in a semiconductor substrate. The gate structure includes a gate dielectric and a contact or gate electrode. The gate contact generally includes metal or doped polysilicon or polysilicon germanium (SiGe) and is formed over the gate dielectric, which is itself formed over the channel region. The gate dielectric is an insulator material, which prevents large currents from flowing from the gate electrode into the channel when a voltage is applied to the gate contact, while allowing an applied gate voltage to set up an electric field within the channel region in a controllable manner.
Transistors are physically very small in many cases, whereby many such devices may be formed on a single-crystal silicon substrate (which can include a base semiconductor wafer and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith) and interconnected in an integrated circuit. Nevertheless, the size of the transistors and other electrical components is continually decreasing to improve device density. However, certain properties of the materials utilized to form the transistors limit the size to which the transistors can be reduced. By way of example, properties of silicon dioxide (SiO
2
), which is commonly used to form the layer comprising the gate dielectric in transistors, can limit the degree to which the thickness of the gate dielectric can be reduced. For instance, extremely thin SiO
2
layers allow for significant gate leakage currents due to direct tunneling of charge carriers through the oxide. Thus, it has been found that operating parameters may change dramatically due to slight variations in gate dielectric thickness.
Furthermore, thin gate dielectric layers are known to provide poor diffusion barriers to impurities. Thus, for example, extremely thin SiO
2
gate dielectric layers suffer from high boron penetration into the underlying channel region during doping of the gate electrode and source/drain regions. Such doping also degrades the gate oxide, rendering it more susceptible to leakage. Previous efforts at device scaling have focused on the addition of nitrogen into the silicon dioxide gate dielectric, however, recent efforts have focused on alternative dielectric materials that can be formed in a thicker layer than silicon dioxide layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of SiO
2
. The relative performance of such high-k materials is often expressed as equivalent oxide thickness (EOT) because the alternative material layer may be thicker, while providing the equivalent electrical effect of a much thinner layer of SiO
2
. Accordingly, high-k dielectric materials can be utilized to form gate dielectrics, where the high-k materials facilitate a reduction in device dimensions while maintaining a consistency of desired device performance.
High-k dielectrics have also been found to suffer from boron penetration during doping of the overlying gate electrode in PMOS transistors, and such boron contamination negatively impacts the EOT thereof as well as transistor performance parameters. Therefore there is a need for improved transistor devices and methods of manufacture that do not suffer the negative impacts of boron penetration.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, its purpose is merely to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe deters a p-type dopant such as boron that is added to an overlying gate electrode material from diffusing into the layer of silicon or SiGe and into an underlying high-k dielectric layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to inhibit the boron from passing through the silicon or SiGe layer. The silicon or SiGe layer dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).
According to one aspect of the present invention, a method of forming a PMOS transistor initially includes forming a gate dielectric layer over a semiconductor substrate. A silicon or SiGe layer is then formed over the gate dielectric layer. The silicon or SiGe layer is doped with an isolating dopant to inhibit boron from passing through the silicon or SiGe layer and diffusing into the underlying gate dielectric layer. A gate electrode layer is then formed over the silicon or SiGe layer. The gate electrode layer, silicon or SiGe layer and gate dielectric layer are then patterned to form a gate structure. The patterned gate electrode layer is doped with boron to establish a desired work function associated with the transistor, and exposed portions of the substrate adjacent the gate structure are doped to form source and drain regions in the semiconductor substrate on opposite sides of the gate s

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