Use of DQ pins on a ram memory chip for a temperature...

Details Use of DQ pins on a ram memory chip for a temperature... Use of DQ pins on a ram memory chip for a temperature...

2002-05-13

2004-10-26

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

C361S093800, C365S211000

Reexamination Certificate

active

06809914

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of memory chips.
2. Discussion of Related Art
A known integrated memory IC
100
that is a writeable memory of the DRAM type is shown in FIG.
1
. Such a dynamic random access memory (DRAM) chip
100
includes a plurality of memory storage cells
102
in which each cell
102
has a transistor
104
and an intrinsic capacitor
106
. As shown in
FIGS. 2 and 3
, the memory storage cells
102
are arranged in arrays
108
, wherein memory storage cells
102
in each array
108
are interconnected to one another via columns of conductors
110
and rows of conductors
112
. The transistors
104
are used to charge and discharge the capacitors
106
to certain voltage levels. The capacitors
106
then store the voltages as binary bits, 1 or 0, representative of the voltage levels. The binary 1 is referred to as a “high” and the binary 0 is referred to as a “low.” The voltage value of the information stored in the capacitor
106
of a memory storage cell
102
is called the logic state of the memory storage cell
102
.
As shown in
FIGS. 1 and 2
, the memory chip
100
includes six address input contact pins A
0
, A
1
, A
2
, A
3
, A
4
, A
5
along its edges that are used for both the row and column addresses of the memory storage cells
102
. The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A
0
to A
5
into the row address latches
114
. Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A
0
to A
5
into the column address latches
116
. The memory chip
100
has data pin Din that receives data and data pin Dout that sends data out of the memory chip
100
. The modes of operation of the memory chip
100
, such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention.
A variation of a DRAM chip is shown in
FIGS. 5 and 6
. In particular, by adding a synchronous interface between the basic core DRAM operation/circuitry of a second generation DRAM and the control coming from off-chip a synchronous dynamic random access memory (SDRAM) chip
200
is formed. The SDRAM chip
200
includes a bank of memory arrays
208
wherein each array
208
includes memory storage cells
210
interconnected to one another via columns and rows of conductors.
As shown in
FIGS. 5 and 6
, the memory chip
200
includes twelve address input contact pins A
0
-A
11
that are used for both the row and column addresses of the memory storage cells of the bank of memory arrays
208
. The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A
0
to A
11
into the bank of row address latches
214
. Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A
0
to A
11
into the bank of column address latches
216
. The memory chip
200
has data input/output pins DQ
0
-
15
that receive and send input signals and output signals. The input signals are relayed from the pins DQ
0
-
15
to a data input register
218
and then to a DQM processing component
220
that includes DQM mask logic and write drivers for storing the input data in the bank of memory arrays
208
. The output signals are received from a data output register
222
that received the signals from the DQM processing component
220
that includes read data latches for reading the output data out of the bank of memory arrays
208
. The modes of operation of the memory chip
200
, such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention.
It is noted that new generations of SDRAM chips are being optimized for bandwidth. The most common method of accomplishing such optimization is to increase the clocking rate of SDRAM chips. By increasing the clocking rate and shortening operation cycles for normal operations, the consumption of current and power during operations increases. Since the internal temperature of the chip is proportional to the power consumption, increasing the clocking rate will result in an increase ;n the internal temperature of the chip.
It is known that there are circumstances where the heat generated in SDRAM chips optimized for bandwidth exceeds the maximum amount of heat that the chip package can dissipate. In most cases, the extent of time at which the generated heat exceeds the maximum amount of heat that can be dissipated is so short that the thermal constant of the chip package is sufficiently high in value so as to prevent destruction of the SDRAM chip.
SUMMARY OF THE INVENTION
One aspect of the present invention regards a method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit that has a data pin, generating a temperature data signal based on the sensing, implementing a temperature sensing protocol and supplying the temperature data signal to the data pin based on the temperature sensing protocol.
The above aspect of the present invention provides the advantage of preventing the thermal destruction of a memory chip.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.


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