Use of data latches in cache operations of non-volatile...

Details Use of data latches in cache operations of non-volatile... Use of data latches in cache operations of non-volatile...

2007-04-17

2007-04-17

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185120, C365S189050, C365S185290, C365S185030, C711S140000

Reexamination Certificate

active

11097590

ABSTRACT:
Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

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