Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-07-16
2003-02-11
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S119000, C236S10100B
Reexamination Certificate
active
06518906
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to Digital-to-Analog Converter (hereinafter “DAC”) technology. Specifically, the invention proposes a system for improving the performance of a DAC.
BACKGROUND OF A PROBLEM
FIG. 6
shows a single-bit cell in a standard CMOS current-steered Digital-to-Analog Converter (DAC). In this circuit, m
1
and m
2
form a cascode current source, where the DC bias voltages V
B1
and V
B2
are generated by a dedicated bias generator (not shown). The DC current which is output by this current source is “steered” to either the R
LP
or the R
LN
load resistor, thus either increasing or decreasing the differential output voltage V
OUT
, by a source-coupled differential pair consisting of transistors m
3
and m
4
.
In a “thermometer-coded” DAC, with an N-bit digital input, 2
N
−1 of the bit cells shown in
FIG. 1
are connected in parallel; See “An 80 MHz 8-bit CMOS D/A Converter”, by T. Miki et. al., IEEE Journal Solid-State Circuits, vol. SC-21, No. 6, December 1986. In this case, each bit cell represents one least-significant bit (LSB). Thus, if the DAC input increases or decreases by one LSB, then the logical input to one of the bit cells, BIT, is either asserted or de-asserted in order to increase or decrease the output voltage by one LSB (1/(2
N
−1) times its peak-to-peak full scale value). Other known DAC architectures combine bit cells with scaled current sources and scaled device sizes to produce the same DAC functionality with fewer bit cells (for example, an N-bit “binary-weighted” DAC requires only N bit cells; See “Principles of Data Conversion System Design”, by Behzad Razavi, 1995, IEEE Press, p. 90. Although each of these architectures has advantages and disadvantages, the performance of each is fundamentally limited by the performance of a single-bit cell.
Accordingly, this invention improves the performance of a single-bit cell in a DAC.
SUMMARY OF THE INVENTION
This invention improves the performance of a single-bit cell in a DAC by decoupling the voltage swing across the load resistors from the output of the current steering device. The invention provides for an electrical circuit including a first load resistor R
1
and a second load resistor R
2
, a current steering circuit, and a decoupling circuit operably coupled between the current steering circuit and the resistors R
1
, R
2
. The current steering circuit steers at least part of a current I
1
through a circuit path towards either the first resistor R
1
or the second resistor R
2
. The decoupling circuit decouples voltage swings across the load resistors R
1
, R
2
from the current steering circuit.
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Takahiro Miki et al. “An 8-MHz 8-bit CMOS D/A Converter” IEEE Journal vol. SC-21, No. 6, Dec. 1986, pp. 983-988.*
David B. Ribner et al. “Design Techniques for Cascoded CMOS Op Amps with Improved PSRR and Common-MMode Input Range” IEEE Journal, vol. SC-19, No. 6, Dec., 1984, pp. 919-925.*
Mohammed Ismail and Terri Fiez, “Analog VLSI Signal and Information Processing”, McGraw-Hill, Inc.*
Behzad Razavi, Principles of Data Conversion System Designs, IEEE Press, copyright 1995, pp. 90-95.
Abel Christopher J
Anidjar Joseph
Ju Peicheng
Agere Systems Guardian Corp.
Nguyen John
Young Brian
LandOfFree
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