Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-03-23
2001-02-06
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C250S310000
Reexamination Certificate
active
06184696
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
FEDERALLY SPONSORED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
The present invention relates to testing individual integrated circuits. In particular, the present invention relates to selectively testing individual chips on a wafer containing multiple chips.
Integrated circuits, and in particular semiconductor integrated circuits, are manufactured by fabricating several individual die or chips on a wafer. The die on a single wafer are typically identical. After fabrication, the wafer is cut up into the individual die. The process of cutting or sawing the wafer into the individual die is called “dicing” the wafer. After the wafer is diced, the individual die are then packaged.
Before the wafer is cut into the individual die, the manufacturer may desire to test the individual die. Such testing permits the manufacturer to discard non-functional die prior to incurring the expense of packaging such defective die.
Typically the individual die are tested by contacting each die on the wafer with a probe device. The probe device contacts test contact pads fabricated on each die, activates the circuitry on the die, and executes a test of the chip. The die failing the test are marked, and are discarded after the wafer is diced.
The current testing methods require that physical probes must be designed and prepared for each different die design, as the points at which the probes must contact the die are different for each die design. The different designs additionally require that the chip tester be physically reconfigured each time a different die design is to be tested.
SUMMARY OF THE INVENTION
The present invention is a method of, and apparatus for, wirelessly testing individual die on a wafer containing multiple individual die or integrated circuits.
The method of testing incorporates selectively activating a selected die on the wafer. The die may be activated by being impacted by electromagnetic radiation having at least a first predetermined energy level. The method of activating the selected die includes directing first and second beams of electromagnetic energy toward the die. Each of the first and second beams of electromagnetic energy individually has less than the first energy level required to activate the die. The method further includes directing the first and second beams of the electromagnetic energy so that they overlap on the first die. The first and second beams overlap on the first die in a region of overlap. In the region of overlap, the first and second beams impact the die with an energy level greater than the first energy level required to activate the die.
The method may additionally include detecting electromagnetic radiation radiated by the die when the die is activated by the energy of the first and second beams of electromagnetic energy.
An apparatus for testing integrated circuit die includes a first source of electromagnetic energy for generating a first beam of electromagnetic energy, and a first deflector for the directing the first beam toward the integrated circuit die to be tested. The test apparatus additionally includes a second source of electromagnetic energy for generating a second beam of electromagnetic energy and a second deflector for directing the second beam toward the integrated circuit die, so that the second beam overlaps the first beam on the integrated circuit die. The test apparatus additionally includes a detector for detecting electromagnetic radiation emitted by the integrated circuit die.
REFERENCES:
patent: 4851768 (1989-07-01), Yoshizawa et al.
patent: 5006795 (1991-04-01), Yoshizawa et al.
patent: 5093572 (1992-03-01), Hosono
patent: 5576542 (1996-11-01), Kaga
patent: 5892224 (1999-04-01), Nakasuji
patent: 04343245 (1992-11-01), None
Andrews, Jr. Warner B.
Hale Kelly H.
Henderson P. Michael
Johnston James W.
Siann Jonathan I.
Conexant Systems Inc.
Metjahic Safet
Snell & Wilmer L.L.P.
Tang Minh
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