Patent
1995-02-10
1997-06-17
Chan, Eddie P.
395489, 39518203, 39518212, G06F 1120, G06F 1216
Patent
active
056405308
ABSTRACT:
A method and system for controlling data flow in a storage subsystem containing multiple cache and/or multiple NVS elements based on the operability of the cache arrays and NVS arrays. In a data processing system having a storage controller connecting a plurality of host processors and a plurality of storage devices, this invention provides a method and architecture for managing multiple storage elements within the controller, without a degradation in subsystem performance and without data integrity problems. A set of configuration registers is utilized by the microcontroller to direct cache and NVS access to the proper storage array. A configuration table is loaded with status information concerning the memory arrays at Initial Microcode Load(IML) and this information is periodically updated during controller operation. The microcode can then either directly load the entries in this table into the configuration registers or the microcode can directly reference the table to determine available resources and make the appropriate decisions.
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Beardsley Brent Cameron
Knowlden Ronald Robert
Spear Gail Andrea
Anderson F. E.
Bragdon Reginald G.
Chan Eddie P.
International Business Machines - Corporation
Sullivan R. M.
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