Amplifiers – With semiconductor amplifying device – Including field effect transistor
Reexamination Certificate
2007-04-03
2007-04-03
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including field effect transistor
Reexamination Certificate
active
11409311
ABSTRACT:
Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.
REFERENCES:
patent: 4163947 (1979-08-01), Weedon
patent: 4240068 (1980-12-01), Handy
patent: 4259582 (1981-03-01), Albert
patent: 4272759 (1981-06-01), Handy
patent: 4471341 (1984-09-01), Sauer
patent: 4472648 (1984-09-01), Prentice
patent: 4763105 (1988-08-01), Jenq
patent: 4783783 (1988-11-01), Nagai et al.
patent: 4851792 (1989-07-01), Ochiai et al.
patent: 4935702 (1990-06-01), Mead et al.
patent: 4958123 (1990-09-01), Hughes
patent: 4962380 (1990-10-01), Meadows
patent: 5166562 (1992-11-01), Allen et al.
patent: 5177697 (1993-01-01), Schanen et al.
patent: 5243347 (1993-09-01), Jackson et al.
patent: 5270963 (1993-12-01), Allen et al.
patent: 5296752 (1994-03-01), Groeneveld et al.
patent: 5376935 (1994-12-01), Seligson
patent: 5543791 (1996-08-01), Riggio, Jr.
patent: 5557272 (1996-09-01), Riggio, Jr.
patent: 5627392 (1997-05-01), Diorio et al.
patent: 5666118 (1997-09-01), Gersbach
patent: 5684738 (1997-11-01), Au et al.
patent: 5689205 (1997-11-01), Hughes et al.
patent: 5710563 (1998-01-01), Vu et al.
patent: 5760616 (1998-06-01), Vallancourt
patent: 5763912 (1998-06-01), Parat et al.
patent: 5773997 (1998-06-01), Stiegler
patent: 5790060 (1998-08-01), Tesch
patent: 5793231 (1998-08-01), Whittaker
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5870044 (1999-02-01), Dell'ova et al.
patent: 5870048 (1999-02-01), Kuo et al.
patent: 5875126 (1999-02-01), Minch et al.
patent: 5892709 (1999-04-01), Parris et al.
patent: 5898613 (1999-04-01), Diorio et al.
patent: 5914894 (1999-06-01), Diorio et al.
patent: 5933039 (1999-08-01), Hui et al.
patent: 5939945 (1999-08-01), Thewes et al.
patent: 5952891 (1999-09-01), Boudry
patent: 5952946 (1999-09-01), Kramer et al.
patent: 5955980 (1999-09-01), Hanna
patent: 5973658 (1999-10-01), Kim et al.
patent: 5982313 (1999-11-01), Brooks et al.
patent: 5982315 (1999-11-01), Bazarjani et al.
patent: 5986927 (1999-11-01), Minch et al.
patent: 5990512 (1999-11-01), Diorio et al.
patent: 5990816 (1999-11-01), Kramer et al.
patent: 6014044 (2000-01-01), Kramer et al.
patent: 6118398 (2000-09-01), Fisher et al.
patent: 6125053 (2000-09-01), Diorio et al.
patent: 6130632 (2000-10-01), Opris
patent: 6134182 (2000-10-01), Pilo et al.
patent: 6137431 (2000-10-01), Lee et al.
patent: 6144581 (2000-11-01), Diorio et al.
patent: 6172631 (2001-01-01), Tsai et al.
patent: 6191715 (2001-02-01), Fowers
patent: 6320788 (2001-11-01), Sansbury et al.
patent: 6373418 (2002-04-01), Abbey
patent: 6388523 (2002-05-01), Kappes
patent: 6424279 (2002-07-01), Kim et al.
patent: 6496128 (2002-12-01), Wiesbauer et al.
patent: 6559715 (2003-05-01), Frake et al.
patent: 6570518 (2003-05-01), Riley et al.
patent: 6573853 (2003-06-01), Mulder
patent: 6583740 (2003-06-01), Schofield et al.
patent: 6606119 (2003-08-01), Shibata et al.
patent: 6614687 (2003-09-01), Chen et al.
patent: 6624773 (2003-09-01), Wong
patent: 6664909 (2003-12-01), Hyde et al.
patent: 6795347 (2004-09-01), Ausserlechner et al.
patent: 6853583 (2005-02-01), Diorio et al.
patent: 6891488 (2005-05-01), McDaniel et al.
patent: 6898097 (2005-05-01), Dugger et al.
patent: 6909389 (2005-06-01), Hyde et al.
patent: 6965142 (2005-11-01), Diorio et al.
patent: 2002/0089440 (2002-07-01), Kranz et al.
patent: 2003/0045263 (2003-03-01), Wakayama et al.
patent: 2004/0004861 (2004-01-01), Srinivas et al.
patent: 2004/0037127 (2004-02-01), Lindhorst et al.
patent: 2004/0124892 (2004-07-01), Diorio et al.
patent: 2004/0206999 (2004-10-01), Hyde et al.
patent: 2004/0240278 (2004-12-01), Brady et al.
patent: 2005/0104119 (2005-05-01), Diorio et al.
patent: 0 298 618 (1989-01-01), None
Bastos, et al., “A 12-bit Intrinsic Accuracy High-Speed CMOS DAC”, IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 1959-1969.
Bugeja, et al., “A Self-Trimming 14-b 100-MS/s CMOS DAC”, IEEE Journal of Solid-State Circuits, vol. 35, No. 12, Dec. 2000, pp. 1841-1852.
Bugeja, et al., “A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance”, IEEE Journal Solid-State Circuits, vol. 34, No. 12, Dec. 1999, pp. 1719-1732.
Carley, L. Richard, “Trimming Analog Circuits Using Floating-Gate Analog MOS Memory”, IEEE Journal of Solid-State Circuits, vol. 24, No. 6, pp. 1569-1575, Dec. 1989.
Diorio, et al., “A Floating-Gate MOS Learning Array with Locally Computed Weight Updates” IEEE Transactions on Electron Devices, vol. 44, No. 12, Dec. 1997, pp. 1-10.
Diorio, et al., “A High-Resolutions Non-Volatile Analog Memory Cell”, IEEE Intl. Symp. On Circuits and Systems, vol. 3, 1995, pp. 2233-2236.
Gray et al., “Analog-Digital Conversion Techniques for Telecommunications Applications”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 9, 1994, pp. 289-315.
Gray, et al., “Analysis and Design of Analog Integrated Circuits”, Second Edition, University of California, Berkeley, 1984, pp. 66-71.
Hasler, et al., “Single Transistor Learning Synapses”, Cambridge, MA, The MIT Press, 1995, pp. 817-824.
Hasler, et al., “Single Transistor Learning Synapse with Long Term Storage”, IEEE, 1995, pp. 1660-1663.
Hyde, et al.; “A Floating-Gate Trimmed, 14-Bit, 250 Ms/s Digital-to-Analog Converter in Standard 0.25 um CMOS”, Impinj, 2002 Symposium on VLSI Circuits, Honolulu HI; pp. 328-331.
Partial International Search for International Application No. PCT/US03/31792, date mailed Apr. 2, 2004.
Pelgrom et al., “Matching Properties of MOS Transistors”, IEEE Journal of Solid State Circuits, Oct. 1989.
Temes “Delta-Sigma Data Converters”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 10, 1994, pp. 317-339.
Tille, et al., “A 1.8-V MOSFET-Only Σ Δ Modulator Using Substrate Biased Depletion-Mode MOS Capicitors in Series Compensation”, IEEE, Journal of Solid-State Circuits, vol. 36, No. 7, Jul. 2001, pp. 1041-1046.
Tsividis, et al., “Continuous-Time MOSFET-C Filters in VLSI”, IEEE Transactions on Circuits and Systems, vol. CAS-33, No. 2, Feb. 1986, pp. 125-140.
Tsividis et al., “Continuous-Time Filters”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 6, 1994, pp. 177-211.
Van der Plas, et al., “A 14-bit Instrinsic Accuracy Q2Random WalkCMOS DAC”, IEEE Journal of Solid-State Circuits, vol. 34, No. 12, Dec. 1999, pp. 1708-1718.
Vittoz, “Dynamic Analog Techniques”, Design of MOS VLSI Circuits for Telecommunications, 1985, pp. 145-170.
Vittoz, “Dynamic Analog Techniques”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 4, 1994, pp. 97-124.
Yoshizawa, et al., “MOSFET-Only Switched-Capicator Circuits in Digital CMOS Technology”, IEEE Journal of Solid-State Circuits, vol. 34, No. 6, Jun. 1999, pp. 734-747.
Colleran William T.
Cooper Scott A.
Diorio Christopher J.
Humes Todd E.
Oliver Ronald A.
IMPINJ, Inc.
Mottola Steven J.
Shami Khaled
Thelen Reid Brown Raysman & Steiner LLP
LandOfFree
Use of analog-valued floating-gate transistors for parallel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Use of analog-valued floating-gate transistors for parallel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of analog-valued floating-gate transistors for parallel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3741236