Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2000-08-31
2003-10-28
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000
Reexamination Certificate
active
06638831
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the preparation of semiconductor packages. In one aspect, the invention relates to singulation of a plurality of interconnected semiconductor packages into separate semiconductor packages. In another aspect, the invention relates to singulation of semiconductor packages using a reference fiducial, and more particularly, to the use of a reference fiducial to control and monitor singulation of a semiconductor package.
BACKGROUND OF THE INVENTION
Chips that are to be used in a circuit or electronic product typically have metal interconnects that are fragile and thin (often on the order of 1.5 &mgr;m in thickness or less). As such, chips are typically attached to a semiconductor package. Packages permit the chip to be connected to a printed circuit board (PCB). Packages also serve to prevent chip breakage and contamination (for example, from substances such as sodium, chlorine and the like), and provide protection from shock and harsh environmental effects, such as moisture. Finally, and perhaps most significantly, packages serve to dissipate heat. In short, packages serve many important and varied functions, and thus, great care must be given to ensure their proper preparation.
Packages must be produced efficiently. Typically, substantial savings of time and money can be achieved in the production of semiconductor packages by handling a plurality of such packages while they are still interconnected as an elongated panel (also called a “package panel”).
While packages are often attached to one another when handled, they typically function or are otherwise used individually. As such, any panel of interconnected packages must be singulated (i.e., separated) into individual packages. A variety of processes exist to singulate such package panels into individual packages. Exemplary processes include: shearing, routing, break-away methods using, for instance, routed tabs as described below, scoring, perforation, dicing, sawing and various punch and die techniques.
A variety of package types exist for connecting chips to a PCB. A dual in-line package (DIP) is probably the most common design. Other packages can be used as well, including, for example: quad packages, thin packages, chip-scale packages, pin grid array packages, and ball ID grid array (BGA) packages. Packages typically include a chip/package connection area to permit the chips to be connected to the lead system of a package via such items as bonding wires, pads, or a series of balls. Selection of the appropriate package depends on a variety of factors. Yet, as electronic devices and the chips that drive their function become more complex, so too must packages increase in their complexity, in order to accommodate such chips.
Ball Grid Array packages are one type of package that can house complex chips. As such, for purposes of this application, “package” shall refer to a Ball Grid Array (or BGA) package. However, it is understood that any package capable of accommodating a similarly complex chip is within the scope of the invention. As the name indicates, a BGA package uses a series of metal solder balls or bumps attached to the bottom side of the package to connect the package to a PCB or electronic device. The number (e.g., 50, 60, 100) and arrangement of balls used in an array (e.g., rectangular array) can vary to convenience depending on a variety of factors, for instance, overall chip or package part complexity.
In the past, the balls of a ball grid array itself have been used as a reference for purposes of singulation, both in terms of determining paths of singulation (also referred to herein, when use in the context of a sawing-type singulation, as “saw streets”). More Specifically, it has been a standard in industry to utilize the balls (or the ball pads to which they are attached) of a ball grid array as a means of comparison vis-a-vis the edge of the package (also called the “ball to edge” standard). In this way, the “ball to edge” standard comparison or test has been used to ensure that overall singulation quality characteristics, for example, edge straightness, precision, accuracy, and ball to edge (or ball pad to edge) offset, are being achieved.
Unfortunately, the balls of the ball grid array can melt or otherwise deform during, for example, package preparation processes. Further, the balls typically tend to stick to the bonding pads, and further still, they tend to deform, then taking on an almost oval or “egg-like” shape. In addition, when the balls are joined to their corresponding ball pads, the ball pads are no longer visible for purposes of control or monitoring. Complicating matters further, the balls can be misplaced ever so slightly, resulting in an inaccurate reference point from which to measure package singulation quality characteristics (again, for instance, edge straightness) within, of course, certain pre-determined tolerance levels. Finally, since balls serve primarily to connect the chip to the PCB, a function wholly separate from singulation, ball placement cannot be adjusted for purposes of singulation alone.
Accordingly, there is a need in the semiconductor industry to provide a singulation method that ensures the production of high quality, precisely sized and shaped, and highly dependable packages, packages having requisite singulation quality characteristics, and the method achieved in a cost-effective and easily-reproducible manner.
SUMMARY
In accordance with one embodiment of the invention, disclosed herein is a semiconductor package panel singulation method using a reference fiducial, the method comprising the steps of:
providing a semiconductor package panel comprising a plurality of interconnected semiconductor packages, at least one of the packages having a reference fiducial formed thereon;
singulating a semiconductor package panel along a path of singulation; and
using the reference fiducial formed on the at least one package to monitor and control the singulating of the semiconductor package panel along the path of singulation.
In accordance with another embodiment of the invention, disclosed herein a semiconductor package panel singulation process using a reference fiducial, the process comprising the steps of:
providing a semiconductor package panel comprising a plurality of interconnected semiconductor packages, at least one of the packages having a reference fiducial formed thereon;
singulating a semiconductor package panel; and
using the reference fiducial formed on the at least one package to monitor and control the singulating of the semiconductor package panel; wherein the steps of singulating the panel and using the reference fiducial are performed substantially simultaneously.
In still another embodiment of the invention, a semiconductor package singulation method is disclosed, the method comprising the step of:
using at least a portion of a reference fiducial formed on at least one package in a semiconductor package panel comprising a plurality of interconnected packages, the fiducial used to monitor and control the semiconductor package singulation method.
In yet still another embodiment of the present invention, a singulation method is disclosed, the method comprising the steps of:
providing a semiconductor package panel having interconnected first and second semiconductor packages;
forming a reference fiducial on at least one of the semiconductor packages;
singulating the package panel into singulated semiconductor packages; and
using the reference fiducial to monitor at least one of a plurality of singulation quality characteristics.
In still another embodiment of the present invention, a fiducial for a singulation method is disclosed, the fiducial comprising:
a metal strip placed on a semiconductor package panel, the package panel comprising a plurality of interconnected semiconductor packages and a support substrate for supporting the metal strip;
wherein the fiducial is structured to ascertain and verify one or more singulation quality characteristics.
In still yet another embodiment of the presen
Chapman Gregory M.
Drussel Zane
Roberts Jay
VanNortwick John
Brewster William M.
Chaudhuri Olik
Micro)n Technology, Inc.
Whyte Hirschboeck Dudek SC
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