Use of a polish stop layer in the formation of metal structures

Details Use of a polish stop layer in the formation of metal structures Use of a polish stop layer in the formation of metal structures

1997-12-31

2000-08-15

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438692, H01L 21302

Patent

active

061036250

ABSTRACT:
The present invention describes a method of forming an interconnect structure. An insulating layer is formed, and then an opening is formed in the insulating layer. Next, a conductive layer is formed over the insulating layer and in the opening. A polishing stop layer is then formed over the conductive layer. The polishing stop layer and the conductive layer are then polished; however, the polishing stop layer is polished at a slower rate than the conductive layer.

REFERENCES:
patent: 5356513 (1994-10-01), Burke et al.
patent: 5516729 (1996-05-01), Dawson et al.
patent: 5633207 (1997-05-01), Yano et al.
patent: 5776833 (1998-07-01), Chen et al.
patent: 5798302 (1998-08-01), Hudson et al.
Joshi, R.V.; "A New Damascene Structure for Submicrometer Interconnect Wiring"; IEEE Electron Device Letters, vol. 14, No. 3, Mar. 1993 pp. 129-132.
Steigerwald, J.M., et al.; "Pattern Geometry Effects in the Chemical-Mechanical Polishing of Inlaid Copper Structures"; J. Electrochem. Soc., Col. 141, No. 10, Oct. 1994; pp.2842-2847.

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