Metal working – Barrier layer or semiconductor device making
Utility Patent
1997-12-16
2001-01-02
Booth, Richard (Department: 2812)
Metal working
Barrier layer or semiconductor device making
C438S302000, C438S257000
Utility Patent
active
06168637
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory and more particularly to a method and system for decoupling source and drain implants without requiring an additional mask.
BACKGROUND OF THE INVENTION
Conventional flash memory cells include a stacked gate, a source, and a drain. Typically, the stacked gate includes a floating gate and a control gate. In addition, the source and drain are typically not identical. The source is conventionally used to erase the memory cell. For example, the source is tailored to allow erasure through tunneling of charges between the source and the gate. Thus, the source is formed such that a portion of the source extends far enough under the gate stack to allow tunneling during erasure. The source also typically has a higher concentration of dopants than the drain. In addition, the sources of a large portion of the memory cells in a sector of flash memory are electrically coupled. The electrical coupling is typically provided by removing and isolation structures separating the sources and implanting a dopant which electrically couples the sources.
The drain is conventionally used to program the memory cell. Because tunneling of charges is not used to program the memory cell, the drain typically does not extend as far under the gate stack as the source. To provide the program voltage electrical contact is made to the drain. Typically, the area on which a drain is formed is longer than the area on which a source is formed so that contact can be made to the drain.
In order to create a flash memory cell, the gate stack is typically formed first. An implant for both the drain and source are then provided. Typically, this implant is an arsenic implant. The drain and source implant is coupled to reduce the number of masks required to form the memory cell. The drain and source implant is typically provided at a direction close to perpendicular to a surface of a semiconductor on which the memory cell is being formed. For example, typical drain and source implants occur at an angle of approximately seven degrees from perpendicular to the surface of the semiconductor. Once the drain and source implant is completed, a layer of photoresist is provided and developed to mask the drain. Any further implants used to form the source are then provided. Examples of such further implants include arsenic and phosphorus.
Although the flash memory cell formed by the above process functions, it would be beneficial to be able to further decouple the drain and source implants. For example, if the drain and source implants were decoupled, different energy implants could be used for the source and drain. Different implant energies correspond to providing the implants at different depths within the semiconductor. Moreover, if the drain and source implant were decoupled, the drain and source could be better tailored to their individual functions. However, introduction of an additional mask should be avoided if possible to prevent complication of processing.
Accordingly, what is needed is a system and method for decoupling the source and drain implants without introduction of an additional mask. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for providing a flash memory cell on a semiconductor. In one aspect, the method and system comprise providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system comprise providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.
According to the system and method disclosed herein, the present invention decouples the source and drain implants without requiring an additional mask.
REFERENCES:
patent: 5366915 (1994-11-01), Kodama
patent: 5674764 (1997-10-01), Liu et al.
patent: 5770502 (1998-06-01), Lee
patent: 5891774 (1999-04-01), Ueda et al.
patent: 5920776 (1999-07-01), Fratin et al.
patent: 6008094 (1999-12-01), Krivokapic et al.
Luning Scott D.
Randolph Mark
Thurgate Timothy J.
Advanced Micro Devices , Inc.
Booth Richard
Sawyer Law Group LLP
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