Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
1997-05-01
2001-02-27
Gorgos, Kathryn (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S664000, C445S050000
Reexamination Certificate
active
06193870
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is related to field emission devices, particularly to gated field emitters, and more particularly to the use of a hard mask in the formation of small diameter via in a gate material layer and a high aspect ratio via in the dielectric layer to enable the formation of a nanofilament or nanocone field emitter self-aligned to the gate.
In recent years substantial effort has been directed to the use of gated field emission devices in flat panel displays and in vacuum microelectronics for radiation hard performance, lower power electron sources for ion cells, and in ultrasensitive chemical sensors. For example, it is forecast that flat panel displays will be a 10-20 billion dollar per year market by the turn of the century. Currently, the flat panel displays primarily involve active matrix liquid crystals, and field emission displays are one of the leading contenders. In field emission cathodes, both the materials of the emitter and the gate, and the geometry of emitter-gate structure are very important. By forming an extremely sharp (needle-like) emitter tip centered in a small grid (gate) hole or via, emission is more uniform among the emitters and the turn-on voltage, at which electron emission is initiated, is lowered.
Recent efforts in the development of gated field emitters having sharp tips have been directed to forming the emitter by electroplating using the grid or gate metal as a counter electrode. Such recent efforts which involved the formation of “nanocones” and “nanofilament” type emitters are exemplified by copending U.S. application Ser. No. 08/847,086, filed May 1, 1997, now U.S. Pat. No. 5,882,503 entitled “Electrochemical Formation of Field Emitters”; copending U.S. application Ser. No. 08/847,087, filed May 1, 1997, now U.S. Pat. No. 5,891,321 entitled “Electrochemical Sharpening of Field Emission Tips”; and copending U.S. application Ser. No. 08/847,088, filed May 1, 1997, pending, entitled “Formation of Nanofilament Field Emission Device With Gate Passivation, each assigned to the same assignee.
These recent efforts have established that electrochemical deposition can be utilized to form nanofilament structures in oxide vias having diameters of 50-200 nm, and aspect ratios (the ratio of the height of the filament to its diamenter) of 5-10 results in a cylindrical shaped nanofilament which is self-aligned to a gate electrode on top of the dielectric. However, in order to make these prior processes more manufacturable, it has been found that it is necessary to passivate the gate structure, see above-referenced application Ser. No. 08/847,088, thereby allowing overplating to occur, thus compensating for nonuniformity in deposition rate. Furthermore, since the electroplating of the emitter may be done on a high resistivity film or resistor layer, adhesion and initiation of the electroplated material is an issue, depending on the composition of the layer on which the emitter is to be deposited. Also, the tip of the electroplated structure must form a sharp point, centered in the gate metal via, substantially in the plane of the gate metal layer.
The formation of gate structures having 100-200 nm diameter using etched nuclear tracks in LEXAN (or other trackable materials) as the mask etched nuclear tracks in ion trackable materials, such as LEXAN, as the mask which generally results in non-uniform and irreproducible gate structures. Furthermore, the gate metal will also be eroded somewhat during the dielectric via etch as a result of sputter yield. This can result in a dielectric via with a sloped sidewall at the top. Finally, if the gate is electropolished back from the edge of the dielectric via, the gate layer suffers a general attack from the electropolish. This would be problemmatic for both electroplated nanofilaments as well as nanocones which are formed by directional deposition through the via.
The present invention enables manufacturing of gated emitters by a process for creating a nanofilament or nanocone field emission device which involves the use of a hard mask layer. The formation of high aspect ratio, electroplated nanofilament structure devices for field emission flat panel displays, for example, requires the formation of a via in a dielectric layer which is self-aligned to a gate metal via structure on top of the dielectric layer. The desired diameter of the via in the dielectric is on the order of 50-200 nm, with an aspect ratio defined by depth divided by via diameter of 5-10. By the use of a hard mask layer on top of the gate metal layer in which the pattern from etched nuclear tracks in trackable material are transferred, the gate structure and the dielectric via may be selectively etched without erosion of the gate layer while either etching the dielectric via or etching back the gate structure or the dielectric. The nanofilament is then electroplated in the via, after which the dielectric is etched back, and the nanofilament sharpened. The process of this invention provides more tolerance in the etching of the gate and dielectric vias, as well as in the electroplating of the nanofilament, dielectric etch back, and nanofilament sharpening. Also, the invention can be effectively utilized in the formation of nanocones.
SUMMARY OF THE INVENTION
It is an object of the invention to form high aspect ratio, electroplated nanofilament structures for field emission displays.
A further object of the invention is to provide for the formation of nanofilament or nanocone field emission devices using a hard mask layer.
Another object of the invention is to provide a process for fabricating sharpened high aspect ratio electroplated emitters which enables more tolerance in the gate via etch, dielectric cavity etch, electroplating and sharpening of the emitters than prior processes.
Another object of the invention is to provide a process for fabricating nanocone emitters which enables more tolerance in the gate via etch and dielectric cavity etch than prior processes.
Other objects and advantages of the present invention will become apparent from the following description and accompanying drawings. Basically, the invention involves a process for the formation of nanofilament field emission devices utilizing a hard mask layer to provide protection of the gate metal layer and greater tolerance in etching the gate via and dielectric via structures, and in electroplating the nanofilament. Also, the invention may enable the sharpening of the tip of the thus formed nanofilament by electrochemically etching using the gate metal as a counter electrode. Further, the invention involves a process for the formation of nanocone field emission devices utilizing a hard mask layer for protecting the gate metal layer and greater tolerance in etching the gate metal via and dielectric via. The process of this invention produces high efficiency field emitters, which are uniform in height and sharpness, and which are particularly applicable for use in flat panel displays and vacuum microelectronics.
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Contolini Robert J.
Morse Jeffrey D.
Carnahan L. E.
Gorgos Kathryn
Smith-Hicks Erica
The Regents of the University of California
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